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RTL Compiler,power estimation

  • Estimating Area & Power of RAM

    Hi, I have .lib file for a RAM and I am using 65nm technology library. I want to use this RAM with my design and calculate Area and Power, but when I syntheisize this RAM area report shows zero utilization. How can I obtain area in terms of number of gates for this RAM?. I like to know if it is possible...
    Posted to Digital Implementation (Forum) by dkhan on Fri, Jun 14 2013
  • Power Difference between Analog Simulation and RTL complier estimation

    Hallo, I am creating a standard cell library. I did analog simulation for cell design and estimated power values for the cells , lets say, NOT, NOR and NAND and I have their power values for static, dynamic, etc. Now based on that I created library file, and used that in RTL omplier for single cell designs...
    Posted to Logic Design (Forum) by GreenGraphene on Mon, Mar 25 2013
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