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RTL compiler

  • User View: “Multi-Mode” Synthesis Approach Includes Power Optimization
    Logic synthesis is an indispensible IC design tool, but its value has a lot to do with how it's used. At a recent Synthesis Community Event at Cadence Dec. 8, Laszlo Borbely-Bartis, staff design engineer at Micron, described a concurrent multi-mode and low-power optimization synthesis flow using...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 5 2012

  • Synthesis User Panel: Power Dominates Front End Design
    What challenges are users facing in front-end IC design these days? According to presenters at a Q&A panel session at a Synthesis Community Event at Cadence Dec. 8, power minimization and optimization are at the top of the list. The panel included three user presenters, an ARM executive, and a Cadence...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 19 2011

  • How Logic Synthesis is Changing
    You probably haven't read much about logic synthesis lately -- it's a mature technology that doesn't attract much attention. But that doesn't mean that new and exciting things aren't happening in synthesis and front-end design, as illustrated by presentations at a Synthesis Community...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 14 2011

  • RC info message
    Hi , When I am inserting my low pwer cells using RTL Compiler I am getting info as "Global Inversion not done". Can any one tell me what is meaning of this. Below is the log file message. Info : Enabled level shifter inserted. [CPF_ISO-204] : Enabled level shifter inserted at port: 'xyz'...
    Posted to Logic Design (Forum) by PradyK on Wed, Sep 21 2011

  • Design for Test (DFT) – New Challenges at Advanced Process Nodes
    Design for test (DFT) doesn't get a lot of press these days, which is unfortunate, because the demands of DFT are dramatically increasing as designers move to smaller lithography nodes. New fault types, test compression, and faster automatic test pattern generation (ATPG) are becoming critical. To...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 15 2011

  • RTL Compiler Cell Recognition Problem
    Hi, I'm having some trouble with getting RTL compiler to recognise more complex standard cells. I am trying to synthesize a simple binary counter with a T flip flop. For some reason the tool is unable to recognise the function of the T flip flop, which was characterized using Encounter Library Characterizer...
    Posted to Logic Design (Forum) by eklikeroomys on Fri, Sep 9 2011

  • RTL Compiler: handling of system verilog interfaces
    Is there a way to prevent RC from bitblasting SV Interfaces ? I would like to be able to write out the elaborated netlist using the write_hdl command but it seems interfaces are always exploded into individual signals.
    Posted to Logic Design (Forum) by Pierre DN on Thu, Aug 25 2011

  • How Imec and Cadence “Wrapped Up” 3D-IC Test
    One of the most challenging aspects of 3D-IC development involves the testing of vertical die stacks with through-silicon vias (TSVs). You have to propagate test data up and down through the stack, verify the functioning of TSVs that are too small to probe, and isolate the individual dies you want to...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Aug 1 2011

  • Synthesizing 'x'
    Hi, look at the following code: always @(*) begin o = 2'bxx; if (a) o = 2'd0; else if (b) o = 2'd1; else if (c) o = 2'd2; else if (d) o = 2'd3; end signal o is DC (don't care) if none of the inputs (a,b,c,d) is asserted. I used the 2'bxx value because (1) it's easier to...
    Posted to Logic Design (Forum) by Tzachi Noy on Mon, Jul 11 2011

  • RTL Compiler: how to get all input ports except clock ports?
    Dear all, I want to add input delay for all input ports (except clock ports), how I can get the list of "all input ports except clock ports"? I know how to get all input ports ([all_inputs]) and how to get all clock ports. But I don't know how to exclude clock ports from all input ports...
    Posted to Logic Design (Forum) by airland on Wed, Jul 6 2011
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