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RTL Compiler

  • What is the equivalent of "synopsys translate_[on|off]

    Synopsys-DC allowes the designers to embed "synopsys translate_off followed by translate_on" in the RTL, to inform DC that the RTL code inside those two statements should not be synthesized. What is the equivalent procedure in RC?
    Posted to Digital Implementation (Forum) by Karthik244 on Sat, Nov 13 2010
  • Re: defined clocks not propagate

    Hi gh: g151 and g152 are synthesized result, not hand-instantiating. its RTL is: assign clk1_inv = (!scan_mode) ? !clk1 : clk1; assign clk2_inv = (!scan_mode) ? !clk2 : clk2; and synthesized result is INVD0HVT g40(.I (scan_mode), .ZN (n_2)); XOR2D0HVT g151(.A1 (n_2), .A2 (clk2), .Z (clk2_inv)); XOR2D0HVT...
    Posted to Logic Design (Forum) by tompy on Tue, Oct 12 2010
  • defined clocks not propagate

    I have a design with clocks defined at root.I can use [get_attrbute propagated_clocks] to get clock propagate at g152/Z, however, I cannot get propagated clock at g151/Z XOR2D0HVT g151(.A1 (n_2), .A2 (clk2), .Z (clk2_inv)); XOR2D0HVT g152(.A1 (n_2), .A2 (clk1), .Z (clk1_inv)); I can also get propagated...
    Posted to Logic Design (Forum) by tompy on Tue, Oct 12 2010
  • command line arguments into RC tcl scripts

    Hi, Is it possible to pass command line arguments (similar to argv in normal tcl scripts) into RC tcl scripts? What I understand is that, when RC is invoked with a '-f' option it invokes the script in its own shell and then invokes the script specified. Supposing that for example, within this...
    Posted to Digital Implementation (Forum) by kasyab on Wed, Sep 8 2010
  • How to blast a selected busse in RC ?

    I have defined in my design a bus wire. In the corresponding verilog it is seen as : wire [3:0]MyBusWire How can I blast this wire in RC ? The nets will become : wire MyBusWire_0, MyBusWire_1, MyBusWire_2, MyBusWire_3; Of course I want to keep all my other busses unblasted ! Patrick.
    Posted to Logic Design (Forum) by PatBoug on Wed, Aug 18 2010
  • Generate statement in RTL compiler version 9.1

    Hi All, I observe that RTL compiler 9.1 does not suppor genvar/generate for constructs. Are there any other alternatives other than this construct that I can use. Thanks, Regards, -Deepak
    Posted to Digital Implementation (Forum) by deeps4 on Thu, Jul 29 2010
  • New Era Of SoC Design – Still Enabled By Logic Designers

    If you were unable to attend Embedded/SoC Enablement Day at DAC, I encourage you to check out Richard Goering's writeup on the new era of SoC design being driven by applications . It describes how Gadi Singer of Intel discussed new TVs that are networked and can run apps on them (which for me is...
    Posted to Logic Design (Weblog) by Jack Erickson on Thu, Jul 8 2010
  • RTL Compiler synthesis problem, memory ports not mapped!!! Generated memory macrocells unusable!!!

    Hello, I am facing a problem during the synthesis (RTL Compiler) which I cannot solve. Here is the problem: Initial status: 1) I have coded my digital design in VHDL. 2) The code has been simulated successfully. 3) In my digital design I also need SRAM and ROM macrocells. a. So I used the ARTISAN memory...
    Posted to Logic Design (Forum) by albares on Wed, Jun 30 2010
  • Illegal assignment to constant

    Hi all, When RTL Compiler do elaborate RTL code, there are a constant value is assigned to the output port. So I get the below error: Error : Illegal assignment to constant. [CDFG-131] [elaborate] : An assignment is made to a constant in file 'dena_asic.v' on line 1712. : A constant value cannot...
    Posted to Logic Design (Forum) by Jinzhe on Tue, Jun 29 2010
  • Re: how to remove constant value flops?

    Hi gh- after a lot of trial run, I finally find the root cause. I set boundary_opto attribute to false, which will disable constant propagation across hierarchies, thus avoid RC to remove those unused registers. After set boundary_opto to true, those registers are removed. BTW, either tied clock to 0...
    Posted to Digital Implementation (Forum) by tompy on Thu, Jun 24 2010
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