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RTL Compiler

  • What does area reported by RTL compiler mean?

    I compile my design to a 45nm library. RTL compiler gives me the following report: Type Instances Area Area % --------------------------------------- sequential 2237 19102.387 15.8 inverter 6982 9830.896 8.1 buffer 535 1255.847 1.0 logic 33180 91031.529 75.1 --------------------------------------- total...
    Posted to Logic Design (Forum) by rexnyu on Fri, Apr 5 2013
  • Set default load in Library generation

    I am creating Standard Cell library. I have generated my own library file. I havent included LEF in the RTL compiler. . 1 )When i estimate power my RTL compiler uses a a load I am unaware of . Is is possible for me to generate library file which defines a default load to all pins unless stated ? . 2...
    Posted to Digital Implementation (Forum) by GreenGraphene on Thu, Mar 28 2013
  • Default Load in RTL Compiler

    I am creating Standard Cell library. I have generated my own library file. I havent included LEF in the RTL compiler. . 1 )When i estimate power my RTL compiler does produce a result but I am uncertain of which load it is assuming d what toggle rate or stimuli is being considered... . 2) I want to set...
    Posted to Digital Implementation (Forum) by GreenGraphene on Thu, Mar 28 2013
  • Problem occurs when reading vcd in RTL Compiler

    Dear all, I need to analyze the power consumption using RTL Compiler based on the VCD file generated by ModelSim. I have two files: gcm.v (This is the main circuit. Module name is "gcm") tb.v (This is the testbench. Module name is "tb", and "gcm" is instantiated as "gcm_tb"...
    Posted to Logic Design (Forum) by rexnyu on Tue, Mar 26 2013
  • Error : Verilog-2001 feature.

    Dear all, I am trying to synthesize a design using RTL compiler (Version v07.10-p004_1 (32-bit), built Jun 18 2007). The tool gives the following error information: always @* begin | Error : Verilog-2001 feature. [VLOGPT-3] [read_hdl] : Implicit event expression in file 'gcm.v' on line 199, column...
    Posted to Logic Design (Forum) by rexnyu on Tue, Mar 26 2013
  • Library Generation

    Hallo, I am creating a standard cell library. Should I generate Netlist including the load caps the schematic. if at all does it make any difference, including and ignoring load cas in Netlist used in Library generation.
    Posted to Custom IC Design (Forum) by GreenGraphene on Mon, Mar 25 2013
  • Power Difference between Analog Simulation and RTL complier estimation

    Hallo, I am creating a standard cell library. I did analog simulation for cell design and estimated power values for the cells , lets say, NOT, NOR and NAND and I have their power values for static, dynamic, etc. Now based on that I created library file, and used that in RTL omplier for single cell designs...
    Posted to Logic Design (Forum) by GreenGraphene on Mon, Mar 25 2013
  • Virtual Clock and Synthesize :)

    Hi everyone, I have couple of doubts. Please help me out. 1. My project is about SRAM design controller. While doing compilation i can able to see(in GUI) all my modules in my design but when i synthesize it one of the sub-module(Adress Decoder-FSM module) is not available. What will be the reason for...
    Posted to Digital Implementation (Forum) by Ram S on Sat, Mar 16 2013
  • Cadence, ARM, Samsung 14nm Test Chip – Collaboration Eases FinFET Digital Implementation

    A recent test chip tapeout using the Samsung 14nm FinFET process revealed significant progress in digital implementation at this new process node. Thanks to deep collaboration and extensive R&D investments in libraries, process, and tools, the digital implementation of the test chip was successfully...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 7 2013
  • C-to-Silicon 12.2 Available for Your Holiday Shopping List

    The winter holiday season is that special time of year when we get bombarded with catalogs, emails, television commercials, banner ads, store displays, and any other method to get our attention on something that somebody is trying to sell. Having been trained as an engineer, I'm able to filter a...
    Posted to System Design and Verification (Weblog) by Jack Erickson on Thu, Dec 13 2012
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