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RTL Compiler

  • New White Paper: Routing Congestion De-Mystified

    Even though routing congestion sounds like a physical design problem, it can cause chip projects to miss schedules, miss performance targets, or result in a larger die size. These are problems that are shared across the project, so if you want to control the success of your chip design project, it is...
    Posted to Logic Design (Weblog) by Jack Erickson on Tue, Jun 16 2009
  • Synthesis Really DOES Need to Change

    A great article appeared in Chip Design a few weeks ago written by Tets Maniwa, “ Synthesis Needs to Change to Serve Modern Chip Design ”. Tets Maniwa is sharp guy. (Those of you designing ICs in the mid/late 1990s probably remember a wonderful magazine called “Integrated System Design”...
    Posted to System Design and Verification (Weblog) by SteveSvoboda on Tue, Jun 2 2009
  • Prototypes, Platforms, and Emulation: Understanding Pros and Cons

    Claims and confusion abound in the marketplace when it comes to three technologies that are widely used for system validation – virtual platforms, emulation, and FPGA prototyping. This posting is an attempt to shed some light by looking at the pros and cons of each. Perspectives given here come...
    Posted to Industry Insights (Weblog) by rgoering on Wed, May 27 2009
  • Synthesis For Modern Chip Design? We have it Right Here...

    Recently somebody pointed out to me a sponsored article that calls for changes to synthesis technology to better serve modern chip design . I fully agree with that call. I was not given a chance to fully agree in the article itself, even though the other synthesis competitors were. Long story. Anyway...
    Posted to Logic Design (Weblog) by Jack Erickson on Thu, May 14 2009
  • Overwriting messages warning in RC

    Hi all, I am getting a whole bunch of these warnings while running RC. Warning : Overwriting messages. Specify a different ID or group to avoid overwriting the existing message. [MESG-2] : Overwriting existing message CLP-206 Can anyone let me know what are these warnings regarding. Thanks.
    Posted to Logic Design (Forum) by shift on Tue, Apr 21 2009
  • Making Sense of Version Numbers

    By Matt Rardon Synthesis Solutions Your Cadence contact tells you that the fix you need is in RC 8.1.201. You ask your internal contact what version of RTL Compiler is installed and you are told that it is 08.10-s203_1. Why the discrepancy? Is this the version that you need? The confusion comes from...
    Posted to Logic Design (Weblog) by Team FED on Tue, Apr 14 2009
  • Constraint Construction: What's Its Function? Part 4 of 4

    This is the last in the series of Constraint Construction blogs ! Today we're going to go over DESIGN RULES and MODES OF OPERATION. DESIGN RULES: Follow them, or else... Often times, these rules are indeed set in the timing library. But perhaps you want sharper transitions in your design to reduce...
    Posted to Digital Implementation (Weblog) by Thom Moore on Thu, Apr 9 2009
  • How To Improve Timing Critical Path Analysis

    By Jack Marshall Sr. Technical Leader Customer Solutions In my first article I wrote about how to generate a Global Timing Debug (GTD) timing report from within RC which would allow you to send all the necessary information to your favorite Cadence AE to facillitate their debugging of your critical timing...
    Posted to Logic Design (Weblog) by Team FED on Tue, Apr 7 2009
  • When Do You Know You've Saved Enough Power?

    This guest post is by David Weir, Lead Design Engineer at Cadence. His paper, "When do you know you've saved enough power?" was voted best-in-track for Logic Design at CDNLive! 2008 Silicon Valley. In this paper we set out to show how designers can measure and explore the impact of implementing...
    Posted to Logic Design (Weblog) by Team FED on Thu, Apr 2 2009
  • Don't Let Power Kill Your Project

    By Diego Hammerschlag Sr. Technical Leader Team FED Power has gone from an imminent threat to the cause of multiple projects across several vendors going under. I have heard of multiple projects that had working RTL prototypes and were far into the backend flow only to find out that the power used would...
    Posted to Logic Design (Weblog) by Team FED on Tue, Mar 31 2009
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