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RTL Compiler

  • RTL compiler - elaborate problem.

    Hi All, When I run rtl compiler I am facing the following error: Error : Invalid operating_conditions name. [LBR-32] [elaborate] : Library has no operating conditions named 'tt_1p2v_25c'. : Use ls to see the valid operating_conditions in the libraries. Error : Error when processing libraries...
    Posted to Digital Implementation (Forum) by sandeepsuhas on Thu, Mar 11 2010
  • When Will We Move From RTL to TLM? I Need to Know!

    My esteemed colleague, Steve Brown, recently wrote a well-thought piece trying to forecast what it will take to move the bulk of design from RTL abstraction to transaction-level modeling (TLM). He uses the gate-level to RTL migration as a reference point so that we can learn from history. He lists a...
    Posted to Logic Design (Weblog) by Jack Erickson on Mon, Mar 8 2010
  • Q&A: How System Design And Verification Can Go “Mainstream”

    System design and verification are part of the RTL flow today, but a higher level of abstraction is now poised to enter the IC design mainstream, according to Ran Avinun, marketing group director for system design and verification at Cadence. In this interview he discusses trends in hardware/software...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Feb 18 2010
  • RTL-to-GDSII Does Not Need Re-tooling - It Needs Re-definition!

    I recently saw a blog post written by a competitor on a purportedly neutral EDA blog, that called for a re-tooling of the RTL-to-GDSII flow. The argument was that for designs 20M gates or larger, you needed to synthesize at the chip-level, and synthesize in conjunction with placement. It also goes on...
    Posted to Logic Design (Weblog) by Jack Erickson on Mon, Jan 25 2010
  • A Visit To Cadence Research Labs, Part 1

    Located a block away from the University of California at Berkeley, the Cadence Research Laboratories provides a unique environment for EDA innovation. But what really goes on there, who works there, and what is the place like? To find out, I recently made the one-hour trip from my Cadence San Jose office...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 18 2010
  • Need help with VHDL libraries in RTL Compiler

    I have an VHDL file that I want to synthesize that starts like this: library ieee; use ieee.std_logic_1164.all; library grlib;(this is a library I define) use.grlib.amba.all; ... when I synthesize with RTL Compiler, it will give me an error like this: "use.grlib.amba.all", no such primary unit...
    Posted to Logic Design (Forum) by yqzhang on Wed, Dec 16 2009
  • How Much Power Are You Leaving On The Table?

    Everybody is looking to reduce their chip's power consumption these days. Often a lot of reduction is needed in order to fit in the desired power envelope. Until now, designers of chips for wireless applications formed the majority of the power management community. These days, it is applicable to...
    Posted to Logic Design (Weblog) by Jack Erickson on Fri, Oct 23 2009
  • Physically-Aware Synthesis: This Time it’s Different

    RTL Compiler Physical has been available for about 2 years now, and we're getting more customers all the time. But we still get the question - how is this different from physical synthesis tools like PKS or Physical Compiler? Those of you that were around 10 years ago when physical synthesis was...
    Posted to Logic Design (Weblog) by Jack Erickson on Fri, Oct 16 2009
  • The Current State of the Art for Physical Synthesis - A Response

    I am posting this detailed blog in response to an article posted on John's Semi-Blog regarding the current state of physical synthesis tools. I too have been involved in this domain all the way back to the Links to Layout methodology of the mid to late 90’s and there is no question that there...
    Posted to Logic Design (Weblog) by jflieder on Mon, Sep 14 2009
  • RTL Power Estimation

    RTL power estimation is a concept that has existed for a long time. The earlier that you can understand where power is consumed by your chip, the easier it is to make a positive impact. The challenge of course is obtaining accurate estimates. It is easy if you are estimating at the chip-level and most...
    Posted to Logic Design (Weblog) by Jack Erickson on Tue, Sep 8 2009
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