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RTL Compiler

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Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test

Memory providers have long used built-in self test (BIST), a technology that builds self-testing circuitry directly into an IC. Logic BIST (LBIST), which tests the functional logic, has been around for a long time too -- but it did not get much traction except for some high-end CPU server and networking...

Posted to Industry Insights (Weblog) by rgoering on Thu, May 10 2012
Propagate a clock from .LIB of a block

Hello all, I am trying to synthesize a module which has a .LIB for one of the blocks. The block has internal clock generators and requires to create a clock on one of the block's ports. I can create the clocks in the top-level by providing hierarchical path. However, I am not able to see the generated...

Posted to Logic Design (Forum) by randomax on Mon, Apr 30 2012
The Technology Behind Encounter 11.1 – Physical Aware Front End Design

In my last blog post I discussed new optimization and modeling technology in the Encounter 11.1 release, announced by Cadence March 5. While that blog post focused on physical IC ("back end") design, the new release also brings more "physical awareness" to front-end design, and that's...

Posted to Industry Insights (Weblog) by rgoering on Tue, Mar 6 2012
RTL Synthesis

Hello.. how to use the spectre library (.scs) files in the synthesis process?..Basically how to convert them into a .lib file?

Posted to Logic Design (Forum) by Orion007 on Thu, Feb 23 2012
TLU support for RC?

Hi, is there a possibility in Cadence RC to use TLU or TLU+ data for synthesis? Alex'

Posted to Logic Design (Forum) by Alex Kli on Wed, Feb 8 2012
unix shell command with slightly complicated commands

Hi, I am trying to use a 'grep' command from RTLCompile to detect a certain pattern in a generated file, and based on the outcome of the grep, do something. To be more precise, I am trying to do the following: 1) First generate a report fiile: report cdn_loop_breaker > loops.txt 2) then trying...

Posted to Logic Design (Forum) by Rashed Islam on Tue, Jan 31 2012
RTL compiler - synthesis

I am traying to synthesize a design to a library with no basic inverters. In general, RTL compiler requires inverters and some other basic cells. and so i will recieve : "synthesis failed- do not have usable inverters". My library have all the logical veriaty of cells except a straight forward...

Posted to Logic Design (Forum) by Ivan13 on Sun, Jan 15 2012
User View: “Multi-Mode” Synthesis Approach Includes Power Optimization

Logic synthesis is an indispensible IC design tool, but its value has a lot to do with how it's used. At a recent Synthesis Community Event at Cadence Dec. 8, Laszlo Borbely-Bartis, staff design engineer at Micron, described a concurrent multi-mode and low-power optimization synthesis flow using...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 5 2012
Synthesis User Panel: Power Dominates Front End Design

What challenges are users facing in front-end IC design these days? According to presenters at a Q&A panel session at a Synthesis Community Event at Cadence Dec. 8, power minimization and optimization are at the top of the list. The panel included three user presenters, an ARM executive, and a Cadence...

Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 19 2011
How Logic Synthesis is Changing

You probably haven't read much about logic synthesis lately -- it's a mature technology that doesn't attract much attention. But that doesn't mean that new and exciting things aren't happening in synthesis and front-end design, as illustrated by presentations at a Synthesis Community...

Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 14 2011

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RTL Compiler

Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test

Propagate a clock from .LIB of a block

The Technology Behind Encounter 11.1 – Physical Aware Front End Design

RTL Synthesis

TLU support for RC?

unix shell command with slightly complicated commands

RTL compiler - synthesis

User View: “Multi-Mode” Synthesis Approach Includes Power Optimization

Synthesis User Panel: Power Dominates Front End Design

How Logic Synthesis is Changing