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RTL Compiler 9.1
Ankush Sood
blog logic design
clock gating
congestion
CPF
defect testing
design for manufacturing
DFT
Digital
false fail
fault model
FED
Jeff Flieder
leakage power
logic desgin
Logic Design
Logic synthesis
Low power
MSV
multi-vt
OPCG
Paul Weil
performance
Physical Prediction
PLE
power
power estimation
power management
power test
QoS
quality
RC-Physical
RE-Spacial
runtime
Spatial
Synthesis
synthesis methodology logic design conformal lec aborts
Test
test escapes
test mode
voltage drop
yield
Logic Design and Test Design: Do they need each other?
Cadence has moved from traditional methods and product offerings for silicon test in favor of a new direction, which answers the title question. In 2008, Cadence recognized that while the Encounter Test product had outstanding quality of results, ease-of-use was lacking. What was perhaps most important...
Posted to
Logic Design
(Weblog)
by
Ed JM
on Sat, Apr 17 2010
Attention RTL Compiler Customers! RC 9.1.200 Is Here
Cadence's synthesis R&D team has an early holiday gift for our RTL Compiler customers. The 9.1.200 release (or as our release management system affectionally calls it, "RC9.1-s203") is now available for download. This release is mainly focused on improvements to the core synthesis engine...
Posted to
Logic Design
(Weblog)
by
Jack Erickson
on Tue, Dec 15 2009
Automatically Identify, Fix, and Prevent Congestion With RTL Compiler Physical
By Ankush Sood Principal Product Engineer Congestion is at the heart of the design closure challenge today. With smaller cell dimensions, increased chip-size and an inclination of design houses to reduce metal layers available for routing (to save costs), designs are getting more congested. The normal...
Posted to
Logic Design
(Weblog)
by
Team FED
on Tue, Aug 11 2009
RTL Compiler's New "Spatial Technology"
By Jeff Flieder Sr. Solutions Manager Over the last few years, RTL Compiler has added a significant number of features targeted toward users that require more physical awareness in their synthesis flow. We first introduced the PLE (Physical Layout Estimation) flow that allows a very low impact way to...
Posted to
Logic Design
(Weblog)
by
Team FED
on Tue, Jul 28 2009
RC Design Explorer: Find the Right Balance of Power and Performance
By Paul Weil Sr. Product Engineer You might be aware that RTL Compiler has had the ability to synthesize top-down to multi-supply multi-voltages (MSMV) and optimize across them. Lowering voltage levels can be a great way to reduce switching power, but it comes at the cost of reducing performance. As...
Posted to
Logic Design
(Weblog)
by
Team FED
on Fri, Jul 24 2009
Now Available: RTL Compiler 9.1.100
I'm pleased to announce that our latest version of RTL Compiler - version 9.1.100 - is now available. This release is a significant upgrade for RC users, I would encourage all our customers to check it out as soon as you can. Some of the highlights include: Quality of Silicon improvements. For timing...
Posted to
Logic Design
(Weblog)
by
Jack Erickson
on Tue, Jun 30 2009
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