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RFIC,cadence

  • Monte carlo analysis

    sir i am ,, using IC 5.10.40 in cadence , ,, I want to make monte carlo analysis for my circuit , but my seniors here are telling that monte carlo is not working here in the version ,, how can i check that ?.. i am just beginer , please reply ,,
    Posted to RF Design (Forum) by rakesh reddy on Thu, Mar 20 2014
  • Issue with Envelope analysis

    Hi, I am simulating the I/Q upconversion using port through envelope analysis. The I input pwl file has samples of a cosine of frequency=5MHz and timestep=0.00125us. The Q input pwl file has samples of value=0 and timestep=0.00125us. The original I, Q pwl files have data upto 2ms. I have attached the...
    Posted to RF Design (Forum) by AparnaG on Sat, Mar 8 2014
  • STM065 536 Design Kit

    Hi, I am new with Cadence community I hope I get some help. I start to work on the STM065 536 design kit which support RFCMOS as well. I have a problems with the suitable model libraries that I should load in the ADE env in order to simulate some simple circuit, that for example has PMOS and NMOS of...
    Posted to RF Design (Forum) by paderborn on Fri, Jan 10 2014
  • Simulating Quadrature Injection locked multiplier (tripler) in Cadence

    Hello Initial information - Using Cadence virtusoso 6.1.5-64b & spectre simulator for designing the followingquadrature injection locked frequency tripler. circuit Diagram - The first input I gave was a 14.66GHz signal The frequency spectrum of the output is as below: ANd then I changed the input...
    Posted to RF Design (Forum) by rohan kr on Sun, Sep 22 2013
  • Re: Different op amp gains using different spectre analysis

    Thanks for reply, However I am facing a very strange problem in my simulation, please help me with this: I am running a parametric simulation to experiment & get the optimal bias current of Op-Amp . For this I gave a list of "I_bias" as "5u 7u " in the parametric analysis window...
    Posted to RF Design (Forum) by OneNewBoy on Thu, Mar 21 2013
  • Different op amp gains using different spectre analysis

    Hi all, I am new to analog design. I have created an op-amp schematic and tried to get open loop gain by 2 ways: (Simulation uses cadence virtuoso) 1) Transient analysis: applied a ramp pulse of 0->VDD to +ve input [with a dc value of VDD/2] and kept -ve input to Vdd/2, then plotted Vout vs V+ and...
    Posted to RF Design (Forum) by OneNewBoy on Wed, Mar 20 2013
  • High frequency quadrature VCO design with good phase noise

    Hello everyone I am a newbie engineer starting my career in RF IC design and working on designing a high frequency VCO (38 GHz) with good phase noise characteristics. I am using Cadence IC6.1.5-64b.500 version and spectre simulator for the schemtic design and simulations. I have to do everything from...
    Posted to Custom IC Design (Forum) by rohan kr on Thu, Mar 29 2012
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