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RF Design

  • Initial DC analysis extremely slow

    I designed a serializer with a PLL. I can do post layout simulation with serializer or PLL separately. When I simulate the whole system, the spectre got stuck at the initial DC analysis. After print out "Trying 'homotopy = gmin' for nodesets.", there is nothing more to output after...
    Posted to RF Design (Forum) by dtgong on Wed, May 27 2009
  • Jurassic Park IV: The Return of ANALOG

    In the lab, no one can hear you scream! When I was getting my BSEE in the 1980s and studying analog and communications, my friends would say, “Why are you studying that old dinosaur, digital is where it’s at!”. Well, far from being consigned to the La Brea tar pit, analog is once again...
    Posted to Custom IC Design (Weblog) by NewYorkSteve on Tue, May 5 2009
  • An Efficient and Fast Verification Flow for Analog Designs Validation using Virtuoso SpectreMDL

    The emergence of sub-micron technologies has enabled today’s designers to include various digital/analog/RF components in a single chip. The complexity of validating such designs has highlighted the necessity for a robust validation methodology and for an appropriate process for running efficient...
    Posted to Custom IC Design (Weblog) by helenet on Mon, May 4 2009
  • Enhanced pnoise Algorithm to Compute Phase-Noise for VCOs with Bandgap Voltage Reference

    Accurate phase-noise characterization is critical in the design of RF and microwave communication systems. SpectreRF ’s shooting PSS/Pnoise analysis has been the golden simulator for the phase-noise simulation, and close correlation between the simulation results and silicon measurement was well...
    Posted to RF Design (Weblog) by helenet on Fri, May 1 2009
  • Getting a Feel for RF

    It was a delight when I read the blog by Bill Schweber of TechOnline's RF DesignLine titled “ Getting some basic RF experience ”. I was surprising pleased that somebody took the time to talk about how one might get the feel for RF. That is because what Bob talks about is more or less...
    Posted to Custom IC Design (Weblog) by TomC on Wed, Apr 29 2009
  • 2009 RFIC Symposium in Boston - Are You Going?

    If you are an RFIC designer then I hope you are planning on attending the 2009 RFIC Symposium and the International Microwave Symposium (IMS) which will be held in Boston, Massachusetts, as the centerpieces of Microwave Week 2009, scheduled from Sunday June 7 through Friday June 12, 2009. The 2009 RFIC...
    Posted to RF Design (Weblog) by TomC on Mon, Apr 27 2009
  • Spectre RF By Any Other Name ...

    It has been a while since I last appende d , hope you are well! It was a little bit difficult to come up with a subject to write about and then recently I was in a meeting where we were talking about transient noise analysis. A designer was discussing the issue of analyzing the noise of a Pipeline ADC...
    Posted to RF Design (Weblog) by Art3 on Wed, Apr 22 2009
  • Setting VIVA Waveform Color Defaults When Using ADE

    I found myself getting a little bit frustrated with some of the default colors that would come up in the VIVA waveform tool while I was plotting from the Analog Design Environment (ADE). After working with Kabir, the Product Engineer for VIVA, I discovered that the colors for the waveform defaults are...
    Posted to RF Design (Weblog) by dondnile on Tue, Apr 21 2009
  • Calculating Large Signal Phase Noise Using Transient Noise Analysis

    My name is Alan Whittaker and I'm in Cadence's Custom IC Proliferation Group. We support Cadence's Technical Field Organization (the AEs) and Cadence customers during the introduction and adoption of new and advanced EDA technologies. I'll be posting here from time to time on methodologies...
    Posted to Custom IC Design (Weblog) by alanw on Thu, Mar 26 2009
  • path to PLL_workshop of Noise Aware PLL Design Flow

    hello, where is the folder of PLL_workshop? Is it with mmsim71 or ic5141? we have mmsim71 and ic5141_usr5 here.
    Posted to RF Design (Forum) by DZhu on Sun, Mar 22 2009
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