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RC

EDPS Workshop – a Review of FinFET Parasitic Extraction Challenges

There's a lot of excitement about the use of FinFETs at advanced process nodes, and no wonder, given their potential power and performance advantages over planar transistors. But CAD and methodology challenges remain, particularly when it comes to parasitic extraction. FinFET extraction challenges...

Posted to Industry Insights (Weblog) by rgoering on Mon, Apr 29 2013
Videos, Presentations Highlight Front-End IC Design Methodologies

Want to know how other designers are solving front-end IC design challenges, and what Cadence R&D is doing to help? The Front-End Design (FED) Technology Summit, held at Cadence San Jose headquarters Dec. 6, 2012, provided some helpful answers. Presentations and videos from most of the sessions are...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 9 2013
10nm and 14nm FinFETs Pose Challenges – But Collaboration Brings Solutions

10nm and 14nm FinFET design will have a lot of challenges, but collaboration among semiconductor ecosystem partners is finding solutions, according to a presentation given at the Common Platform Technology Forum Feb. 5, 2013. The presentation was given by Vassilios Gerousis (right), distinguished engineer...

Posted to Industry Insights (Weblog) by rgoering on Tue, Feb 12 2013
ARM Blog Tells Story of a 20nm Cortex-M0 Test Chip

All 20nm test chips are learning experiences, and a recent tapeout of a 20nm Cortex-M0 test chip by ARM engineers was no exception. Completed in June 2012, the test chip design used a Cadence digital implementation flow. The story of the test chip is told in a new guest partner blog (I'm the "guest"...

Posted to Industry Insights (Weblog) by rgoering on Tue, Nov 27 2012
LEC issue - "elaborate" vs. "synthesize -to_generic"

Hi, When running LEC on golden-(elaborate) and revise-(synthesize -to_generic) getting one NON-EQ compare point. The following RC attributes didn't help: set_attribute prune_unused_logic false [find [find / -inst TOP/SUB ] -ignorecase -pin *] set_attribute prune_unused_logic false [find [find / ...

Posted to Logic Design (Forum) by Yemelya on Fri, Oct 5 2012
Designer View – Low-Power IC Design Challenges and Solutions

The IC physical design team at Marvell Technology Group Ltd. has a tough challenge. They're under a lot of pressure to minimize power consumption as much as possible, while getting products out the door quickly. In a recorded presentation at the Cadence web site, Murali Natarajan, senior physical...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 23 2012
Tips for Fixing Timing Violations and Adopting Best Practices for Optimization with RTL Compiler

Best Practices for Optimization What should be my considerations while preparing data? Libraries, HDL, Constraints... A good result from a synthesis tool depends greatly on the input data. An old saying "garbage in garbage out" is also true for RTL Compiler. Before attempting to run synthesis...

Posted to Logic Design (Weblog) by SumeetAggarwal on Tue, Aug 7 2012
Propagate a clock from .LIB of a block

Hello all, I am trying to synthesize a module which has a .LIB for one of the blocks. The block has internal clock generators and requires to create a clock on one of the block's ports. I can create the clocks in the top-level by providing hierarchical path. However, I am not able to see the generated...

Posted to Logic Design (Forum) by randomax on Mon, Apr 30 2012
power estimation using rc

Hi all, I got a question about power estimation using cadence rc. I have two designs in HDL. Both of then have a 1-bit full adder. After synthsis, and post-simulation with the netlist with the same test data, I found the output toggle rate of these two 1-bit full adder are different, even though they...

Posted to Logic Design (Forum) by RCsyn on Wed, Feb 29 2012
RC area information

Hi ! I have a very general question concerning the RC : Where does the RC get the area information from after the elaboration process? Is it just estimated without concerning the technology libraries? Thank for your support, Alex'

Posted to Logic Design (Forum) by Alex Kli on Mon, Sep 19 2011

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RC

EDPS Workshop – a Review of FinFET Parasitic Extraction Challenges

Videos, Presentations Highlight Front-End IC Design Methodologies

10nm and 14nm FinFETs Pose Challenges – But Collaboration Brings Solutions

ARM Blog Tells Story of a 20nm Cortex-M0 Test Chip

LEC issue - "elaborate" vs. "synthesize -to_generic"

Designer View – Low-Power IC Design Challenges and Solutions

Tips for Fixing Timing Violations and Adopting Best Practices for Optimization with RTL Compiler

Propagate a clock from .LIB of a block

power estimation using rc

RC area information