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  • How to avoid unwanted removal of logic during synthesis

    Hi All, I am synthesizing a processor design with RTL compiler. The synthesized netlist works fine and contains all necessary logic when I set a loose clock constraint (5000ps). But when I synthesized the same files with a tighter clock constraint (1800- 3000ps) the RTL compiler meets the constraint...
    Posted to Logic Design (Forum) by dkhan on Sun, Jul 7 2013
  • RC: clock gating

    Hello, What is the right way to insert clock gating in RC script? I found the following flag: set_attribute lp_insert_clock_gating true Is it enough or there is something else needed? How should I translate the following instructions from DC for RC: set_clock_gating_style -sequential_cell latch \ -control_point...
    Posted to Logic Design (Forum) by Yemelya on Wed, Jun 29 2011
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