Home > Community > Tags > RC/HAL
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *


  • Synthesizing 'x'

    Hi, look at the following code: always @(*) begin o = 2'bxx; if (a) o = 2'd0; else if (b) o = 2'd1; else if (c) o = 2'd2; else if (d) o = 2'd3; end signal o is DC (don't care) if none of the inputs (a,b,c,d) is asserted. I used the 2'bxx value because (1) it's easier to...
    Posted to Logic Design (Forum) by Tzachi Noy on Mon, Jul 11 2011
Page 1 of 1 (1 items)