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Qualcomm,Industry Insights
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Xilinx
Si2 DAC Panel: What Standards are Needed for 3D-ICs?
3D-ICs with through-silicon vias (TSVs) are not yet in volume production, but work has already begun on design standards - and more work is needed soon. An excellent update on work in progress, and a discussion of what's needed, was provided at a Silicon Integration Initiative (Si2) panel discussion...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jun 28 2012
EDA Symposium: Users Cite 3D-IC Design Tool Needs
What's needed to bring 3D-ICs with through-silicon vias (TSVs) - or 2.5D ICs with silicon interposers - into the IC design mainstream and volume production? That question resonated through a day-long session on 3D-ICs at the Electronic Design Processes Symposium ( EDPS ) April 6, 2012 in Monterey...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Apr 9 2012
DVCon Panel Debate – “Build or Buy” Emulation and Prototyping?
Emulation and FPGA-based prototyping are becoming increasingly necessary for complex systems-on-chip, but where are these hardware-assisted tools going to come from? Should you invest the resources to build and maintain your own, or purchase a commercially available solution? In either case, what do...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 7 2012
DVCon User Panelists: Is Low Power Design Worth the Costs?
Much has been written about the specific techniques that IC designers can use for low-power design and verification, but a larger context is missing. What's the end goal, and what are the costs, benefits, and challenges of implementing power management? In a lively panel discussion at the DVCon conference...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 29 2012
DAC Panel Calls Off “Battle” Between Prototyping and Emulation
A Design Automation Conference (DAC) panel June 8 looked like it was destined for controversy. It was titled, "Software-Hardware Verification Battle: Prototyping vs. Emulation." But that battle didn't happen. Instead, most participants agreed that several types of hardware/software integration...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jun 14 2011
DAC Panel: Users Describe Mixed-Signal Verification Challenges, Solutions
Should analog/mixed-signal verification be more like digital verification, with separate verification teams, a methodology like the Universal Verification Methodology (UVM), and metric-driven verification (MDV)? Yes, according to three mixed-signal engineers at a panel discussion at the Cadence EDA360...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 13 2011
3D IC Ecosystem Panel: Different Views, Challenging Questions
The 3D IC supply chain ecosystem is just beginning to emerge, with roles that are currently unclear. So what happens when you bring together representatives from an outsourced assembly and test (OSAT) provider, memory maker, foundry, EDA vendor (Cadence), and a customer? The result: differing perspectives...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Apr 3 2011
DVCon: Mixed-Signal Designers Cite Verification Challenges and Needs
If you want to know how challenging mixed-signal verification really is, the best thing is to listen to the people in the trenches. A March 3 lunch panel at the DVCon conference, sponsored by Cadence, allowed an attentive audience to do just that. The panel included three users and two vendor representatives...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Mar 6 2011
Panelists: FPGA Tool Opportunity is at the System Level
FPGA designers in the past got by with free or low-cost tools, and didn't provide much revenue for EDA companies. According to panelists at DesignCon Feb. 1, those days are going fast. A new era of complex FPGAs is opening a tremendous opportunity for new EDA support, especially at the system level...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 2 2011
Common Platform Forum: A Clearer Path to Advanced Process Nodes
Insights into what you can expect at 32/28nm and below came to the forefront at the Common Platform Technology Forum Jan. 18, a well-attended one-day event in Silicon Valley. One point that caught my attention is that IBM is turning to a "gate last" high-k metal gate (HKMG) technology at 20nm...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 18 2011
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