Home > Community > Tags > Qi Wang
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Qi Wang

  • DAC 2013: Accellera Panel Updates Power Format Standards

    In what was billed as a "town hall meeting" about the new IEEE 1801-2013 (UPF 2.1) power intent format standard , the Accellera Systems Initiative sponsored a breakfast panel at the Design Automation Conference ( DAC 2013 ) Monday, June 3. The discussion took a broader look at power intent...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jun 6 2013
  • Insider Story of the New IEEE 1801-2013 (UPF 2.1) Standard

    The IEEE has announced the publication of the new 1801-2013 standard, also known as UPF 2.1, and immediate availability for free download through the IEEE 1801-2013 Get Program . Even though the standard is new to the whole world, for the people of the IEEE working group this standard is finally done...
    Posted to Low Power (Weblog) by QiWang on Fri, May 31 2013
  • Q&A: Qi Wang Updates EDA Power Intent Format Standards

    IC design teams can use one of two formats to express power intent - the Common Power Format (CPF) from the Silicon Integration Initiative ( Si2 ), or IEEE 1801 , also known as the Unified Power Format (UPF). Efforts are now underway to bring the two formats closer together, and Qi Wang, technical marketing...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 20 2013
  • Low-Power Technology Summit Proceedings Now Available

    On October 18, 2012 Cadence held a Low-Power Technology Summit at our San Jose, California headquarters. Experts from Cadence and other leading companies presented the latest low-power design methodologies. Well, it took us a while but you can now view the material via the Low-Power Technology Summit...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, Dec 5 2012
  • Low-Power Design? Brian Bailey Gets It

    Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of editorials, opinion pieces and contributed articles on the subject of low power design. As he...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, May 2 2012
  • System-Level Low Power Design – What Will it Take to Move There?

    While many low-power design techniques are available to IC designers, the greatest potential for power savings is at the system level, where both software and hardware can be considered. So what's standing in the way of system-level low power design, and what needs to happen to make it practical...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 18 2012
  • Cadence Low Power Guru Wins Si2’s Distinguished Service Award

    Normal 0 false false false EN-US X-NONE X-NONE MicrosoftInternetExplorer4 /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:"";...
    Posted to Low Power (Weblog) by Pete Hardee on Fri, Oct 21 2011
  • New Features In CPF 1.1

    This is a guest post by Qi Wang, Sr. Architect for the Cadence Low Power Solution, providing more information on what is contained in the recently-announced CPF version 1.1 . There are many major improvements in the new Si2 CPF version 1.1, and I would like to provide more details on a few of them: Complete...
    Posted to Logic Design (Weblog) by Team FED on Tue, Mar 17 2009
  • Flash: Qi Wang - Cadence Low Power Architect Presenting @ VLSI Conference in India

    Just a short note for those who will be attending the exciting 22nd International conference on VLSI design in India . Don't miss Dr. Qi Wang of Cadence, Senior Architect, who co-authored a paper and is co-presenting at this event @ 9am ! Location: New Delhi, India Date: January 8, 2009 Session:...
    Posted to Logic Design (Weblog) by Kenneth Chang on Tue, Jan 6 2009
Page 1 of 1 (9 items)