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  • Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

    In a recently archived May 2 webinar , speakers from Cadence and Samsung described a 20nm digital design methodology that can manage challenges such as double patterning, variability, and complexity. The webinar discussed EDA tools, physical IP, and 20nm process technologies, and it highlighted a "proof...
    Posted to Industry Insights (Weblog) by rgoering on Mon, May 7 2012
  • QRC Extraction Error (FLTTDTA-109002)

    HI, I'm trying to perform PEX using QRC (EXT10.1) for a small custom design created in Virtuoso (IC6.1.5) using a commercial PDK. I've been following the guide that came with the PDK for performing DRC, LVS, PEX. It has passed DRC and LVS fine using Mentor Calibre (2011.4) however I get the following...
    Posted to Custom IC Design (Forum) by jaw500 on Fri, Jan 20 2012
  • QRC nrd/nsd extraction

    Hi, I am trying to extract the source/drain regions for MOS tranistors. QRC:ext9.14 and assura 410 So I added 'mos_diffusion_parameter_extraction -res fast' and selected 'Extract MOS Diffusion Res' from the QRC Run. After the run the qrc stuck with the error show below: Thanks for your...
    Posted to Custom IC Design (Forum) by dinac on Wed, Sep 7 2011
  • Running QRC with Dynamic Link Momentum cells.

    Hi! I am running QRC on layout that has some Dynamic Link momentum cell. But in config view hierarchical editor does not see the momentum cells so the simulations are not OK. Can somebody advise how to solve this problem?
    Posted to RF Design (Forum) by Aleksus on Sat, Jun 25 2011
  • New Silicon Realization Design Methodology Boosts 3D ICs With TSVs

    Cadence this week (Jan. 31) is announcing a "unified" 3D IC design methodology that drives creation, implementation, and verification across the digital, analog, and packaging domains. It's part of a larger announcement of a digital end-to-end flow. What follows are some more details on...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 31 2011
  • Re: Does Assura version affect QRC

    Upgrade your Assura version or give it a try without Assura altogether. As Andrew said in his post: "... Also you must not have ASSURAHOME set, otherwise the QRC menu does not appear, and instead you access it via Assura->QRC" Cheers, Riad.
    Posted to Custom IC Design (Forum) by Riad KACED on Wed, Oct 7 2009
  • Re: Does Assura version affect QRC

    Hi, Andrew has answered a very similar question in this forum. Check it out here . Cheers, Riad.
    Posted to Custom IC Design (Forum) by Riad KACED on Wed, Oct 7 2009
  • Does Assura version affect QRC

    Hi, I'm trying to setup QRC and I've followed the manual by adding the following: In the csh file: setpath = ($EXT_8_1_4/tools/bin $path) In the cds file: setenv QRC_HOME usr/cds/ext-8.1.4 However QRC is not showing up in the menu on the virtuoso layout editor. I'm using IC 5.1.41 latest...
    Posted to Custom IC Design (Forum) by Jsierra on Wed, Oct 7 2009
  • QRC extraction problem

    Hi I am using Assura(V3.2)-QRC(EXT8.1) flow for the extraction. When I started the run, it was stopping while running capgen (Techgen -trans) by giving error number CAPGEN-41414. why it is running Techgen automatically. I have all the files which is used for extraction. Where can I find the man of the...
    Posted to Custom IC Design (Forum) by chiatubek on Tue, May 12 2009
  • setting QRC UI in Virtuoso layout editor

    Hi, I am using QRC (EXT8.1 version) for extraction. I have set the QRC_HOME varible properly. In the $path I set this varible before CDS_HOME. When I open Layout editor, I am not seeing QRC tab in the GUI. I want to see QRC in the Layout editor. Is any seetings I need to do? Please help me Thanks in...
    Posted to Custom IC Design (Forum) by chiatubek on Thu, Apr 30 2009
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