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QRC,Virtuoso

  • TSMC 3D-IC Reference Flow Supports 3D Die Stacking

    An important milestone for any new semiconductor technology is the availability of a foundry EDA reference flow. Such a milestone occurred last week (Sept. 18, 2013) as Cadence and TSMC delivered the latest Cadence 3D-IC reference flow for true 3D die stacking (right). While there has been considerable...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Sep 24 2013
  • IBIS model simulation

    I am designing a Data acquisition system with a Texas instruments ADC, Inamps and a ST micro electronics micro controller. I am getting spice models for my inamps, differential amplifiers etc. so that I could do SPICE simulation. I wish to see the output of my ADC if I am providing an input signal with...
    Posted to PCB Design (Forum) by niranjan madha on Wed, Apr 17 2013
  • 10nm and 14nm FinFETs Pose Challenges – But Collaboration Brings Solutions

    10nm and 14nm FinFET design will have a lot of challenges, but collaboration among semiconductor ecosystem partners is finding solutions, according to a presentation given at the Common Platform Technology Forum Feb. 5, 2013. The presentation was given by Vassilios Gerousis (right), distinguished engineer...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Feb 12 2013
  • How Cadence Helps Universities Build EDA Infrastructures

    Many EDA companies, including Cadence, have university programs that make it easier for academia to acquire tools. But what about the software/hardware infrastructure that supports those tools? In this era of budget shortfalls, university compute infrastructures are under severe stress. Recently the...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Nov 7 2012
  • ARM TechCon: Inside Story of a 14nm FinFET Tapeout

    The next frontier in semiconductor design is the 14nm process node, and it will come with a new type of transistor, the FinFET. 14nm FinFET technology moved closer to reality at the ARM TechCon conference Oct. 30, 2012, where a Cadence sponsored technical session announced a 14nm test chip tapeout using...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 31 2012
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
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