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Pspice convergence transient simulation

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  • Pspice convergence aid?

    In some tools (eg Hspice), a common technique to help convergence of transient sims of mixed logic + analog is to "buffer" PULSE sources (for incoming logic signals) thru a piecewise-linear voltage-controlled voltage-source ("PWL" similar to DC TABLE) that forces linear interpolation...
    Posted to Cadence Academic Network (Forum) by jfasig on Tue, Sep 4 2012
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