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Power

  • System-Level Low Power Design – What Will it Take to Move There?
    While many low-power design techniques are available to IC designers, the greatest potential for power savings is at the system level, where both software and hardware can be considered. So what's standing in the way of system-level low power design, and what needs to happen to make it practical...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 18 2012

  • Don’t Blow Up Your Chip on the Tester!
    The photo at right shows a test socket and chip destroyed by thermal runaway. Can this really happen? Yes, it can and it sometimes does, if test power is significantly greater than functional power. To get a handle on this problem I talked to Bassilios Petrakis, product marketing director for Design...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 26 2012

  • CDNLive! Keynote – New Horizons for ARM Based SoCs

    30 billion ARM-based chips have shipped over the last 20 years, but ARM isn't stopping there. ARM is looking beyond cell phones and mobile devices and pursuing new opportunities in the server, home entertainment, and automotive marketplaces, according to Tom Lantzsch (right), executive vice president...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 15 2012

  • EDA CEOs Speak Out: 3D-ICs, IP Integration, Low Power, and More
    What's driving the EDA industry today and where is it headed in the near future? Some high-level answers to these questions came from the EDA Consortium (EDAC) annual CEO Forecast panel Feb. 29, 2012. EDA industry leaders shared their views about 3D-ICs, SoC integration, power management, industry...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 5 2012

  • Webinar Report: Power-Aware Mixed-Signal Verification
    Most of the discussion about low-power design techniques has focused on digital circuits. However, nearly all systems-on-chip (SoCs) are mixed-signal, and the way in which analog and digital circuitry interact has a huge impact on overall power consumption. Thus, low power (or "power aware"...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 25 2012

  • What’s Next in Low Power?

    Low power has become a major consideration in chip design in almost all applications. One major achievement of the industry over the past a few years is the alignment on the low power design methodology, which was considered as the biggest hurdle to automate advanced low power design techniques. No matter...
    Posted to Low Power (Weblog) by QiWang on Tue, Jan 24 2012

  • Webinar Report: Solving Mixed-Signal Power Grid Challenges
    Complex analog/mixed-signal ICs pose many power grid design and analysis challenges. Unanticipated IR drop and electromigration problems are commonplace, and they significantly impact circuit behavior. But as a recently archived webinar shows, there are a number of ways to minimize these problems, even...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 11 2012

  • Synthesis User Panel: Power Dominates Front End Design
    What challenges are users facing in front-end IC design these days? According to presenters at a Q&A panel session at a Synthesis Community Event at Cadence Dec. 8, power minimization and optimization are at the top of the list. The panel included three user presenters, an ARM executive, and a Cadence...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 19 2011

  • How Logic Synthesis is Changing
    You probably haven't read much about logic synthesis lately -- it's a mature technology that doesn't attract much attention. But that doesn't mean that new and exciting things aren't happening in synthesis and front-end design, as illustrated by presentations at a Synthesis Community...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 14 2011

  • Three Die Stack -- A Big Step “Up” for 3D-ICs with TSVs
    A major advancement in 3D-IC through-silicon via (TSV) design will be unveiled Tuesday (Dec. 13) as representatives of CEA-LETI and ST-Ericsson describe the development of a three-die stack with wide I/O memory and logic. This tapeout is the result of a collaboration between these two organizations and...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Dec 13 2011
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