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Power amplifier

  • Can a beginner ask here for some help?

    Hi, I am a student at local faculty of Electrical Engineeing, and I just recently started using Cadence Virtuoso. The thing is, I am also employed, and I'm attending this course in RF electronics at the department which I don't belong to. We had a couple of lab exercises till now, using Virtuoso...
    Posted to RF Design (Forum) by Lajka on Thu, May 8 2014
  • Double Exponential Current Pulse In Virtuoso

    Sir, Is it possible to model a double exponential current pulse ( used for representing Single Event Itransients) in Cadence Virtuoso?. It would be helpful if you could explain the method for getting the same. Yours faithfully Aravind
    Posted to RF Design (Forum) by aravindkvarier on Thu, Apr 17 2014
  • Issue with Envelope analysis

    Hi, I am simulating the I/Q upconversion using port through envelope analysis. The I input pwl file has samples of a cosine of frequency=5MHz and timestep=0.00125us. The Q input pwl file has samples of value=0 and timestep=0.00125us. The original I, Q pwl files have data upto 2ms. I have attached the...
    Posted to RF Design (Forum) by AparnaG on Sat, Mar 8 2014
  • ERROR DURING SIMULATION

    Sir, First of all, let me thank u for helping me in my project work, by giving valuble information. We are using BSIM-CMG (DG-MOSFET) model for circuit analyses and earlier, we were getting the output waveforms as well as pss analysis results by using virtuoso 6.1.4 version. But last day, the version...
    Posted to RF Design (Forum) by aravindkvarier on Tue, Mar 4 2014
  • Unable to run PSS Analysis

    Sir, I have used BSIM-CMG107.0.0 Mosfet Compact model for my thesis work. But when I go for pss analysis, an error is shown saying that the behavioural file that you have given is not supported for pss analysis. The model is actually a verilog-A file. It would be grateful if you give me any solution...
    Posted to RF Design (Forum) by aravindkvarier on Tue, Feb 11 2014
  • Power amplifer design advice needed

    Hello, Cadence community, I'm designing an RF power amplifer (PA) and have stumbed on a problem. First of all, the PA has 2 stages - 1st stage is A class, 2nd stage - meant to be AB class. Output matching is precisely fixed to the required frequency. The problem sound like this: I get a maximum amplitude...
    Posted to RF Design (Forum) by Alex Vasjanov on Mon, Sep 30 2013
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