Home > Community > Tags > Power Analysis/ModelSim
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Power Analysis,ModelSim

  • Re: Does clock power included in Power Report ?

    [quote user="grasshopper"] Hi dkhan, unfortunately the answer is "It depends" If you are using a netlist and also annotating all parasitics, you will effectively have the clock tree accounted for but if you do not annotate parasitics or working at RTL level, the answer is mostly not...
    Posted to Logic Design (Forum) by dkhan on Mon, Jul 29 2013
  • using ModelSim/QuestaSim VCD file in RTL compiler

    Hi, I want to use VCD file from QuestaSim 6.0 in RTL compiler to obtain power report. The netlist file I am using in QuestaSim for simulation and VCD file generation is also generated by RTL compiler byt when I run following commands I got no asserted signals in the power result. Does RTL compiler supports...
    Posted to Logic Design (Forum) by dkhan on Tue, Jun 18 2013
Page 1 of 1 (2 items)