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Physical verification,Design for yield

  • Tidbits From TSMC Q209 Earnings Call - 40nm Yield

    Earning calls sure are interesting! Below is an excerpt from the TSMC Q209 call (transcript from seekingalpha). The discussion revolves around the 40nm yield issues and TSMC's ramp to improving the yield. Dr. Liu really hits on a key element of DFM - which is design/layout dependency. Simply put...
    Posted to Silicon Signoff and Verification (Weblog) by wilbur on Fri, Aug 7 2009
  • Getting Good Silicon With More Accurate Timing

    In these difficult economic times, achieving silicon success (functional and meeting specs) within an iteration becomes an even higher priority than before; there might not be a second chance to win that socket or hit that sales window. To that end, there appears to be a heightened interest in variation...
    Posted to Silicon Signoff and Verification (Weblog) by wilbur on Fri, Jan 9 2009
  • DFM in Disguise

    DFM is an overloaded acronym/word. In some design flows, DFM can be found front-and-center and in others, it is just along-for-the-ride. It may be disguised as more rules in a process/rules design manual, or it can be quite explicit in a model-based analysis and optimization flow. But wait, let's...
    Posted to Silicon Signoff and Verification (Weblog) by wilbur on Sat, Jul 12 2008
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