Home > Community > Tags > Physical verification
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email
* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Physical verification

  • GTC Presentation: Cadence Outlines Comprehensive 20nm Design Flow
    The design and manufacturing challenges of 20nm ICs are formidable, and will not be solved by loose collections of point tools. At the recent Global Technology Conference ( GTC ), Cadence presented its view of 20nm challenges and previewed a comprehensive 20nm design methodology that encompasses custom...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 7 2011

  • Tidbits From TSMC Q209 Earnings Call - 40nm Yield
    Earning calls sure are interesting! Below is an excerpt from the TSMC Q209 call (transcript from seekingalpha). The discussion revolves around the 40nm yield issues and TSMC's ramp to improving the yield. Dr. Liu really hits on a key element of DFM - which is design/layout dependency. Simply put...
    Posted to Manufacturability Signoff (Weblog) by wilbur on Fri, Aug 7 2009

  • Assura Foundry Support
    I've been blogging a lot about Assura recently, so I thought I would continue by talking about rule decks. Inside Cadence, we maintain a database that shows which foundries support which process for which products. This means that we can quickly give you an answer if you are considering using a new...
    Posted to Manufacturability Signoff (Weblog) by ChrisClee on Mon, Mar 23 2009

  • Getting Good Silicon With More Accurate Timing
    In these difficult economic times, achieving silicon success (functional and meeting specs) within an iteration becomes an even higher priority than before; there might not be a second chance to win that socket or hit that sales window. To that end, there appears to be a heightened interest in variation...
    Posted to Manufacturability Signoff (Weblog) by wilbur on Fri, Jan 9 2009

  • DFM in Disguise
    DFM is an overloaded acronym/word. In some design flows, DFM can be found front-and-center and in others, it is just along-for-the-ride. It may be disguised as more rules in a process/rules design manual, or it can be quite explicit in a model-based analysis and optimization flow. But wait, let's...
    Posted to Manufacturability Signoff (Weblog) by wilbur on Sat, Jul 12 2008

  • Allow myself...
    In the words of Austin Powers, "Allow myself to..." - well you get the idea. I'm Chris, and I am a Senior Product Marketing Manager for a number of Cadence physical verification, yield analysis and mask design products. I have about 20 years in EDA under my belt. My professional interests...
    Posted to Manufacturability Signoff (Weblog) by ChrisClee on Fri, Jul 11 2008
Page 1 of 1 (6 items)