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Physical verification

  • Taming the Challenges of IC Design

    AUSTIN, Texas--You want the bad news first or the good news about IC design challenges? Let's start with the bad news: As IC design moves into 20nm and 16nm nodes, the challenges facing not only designers but EDA vendors are extraordinary if the industry is to maintain momentum and design productivity...
    Posted to The Fuller View (Weblog) by Brian Fuller on Wed, Jul 24 2013
  • Q&A: Anirudh Devgan Discusses New Cadence Signoff Strategy

    Anirudh Devgan is corporate vice president of R&D for Silicon Signoff and Verification, which is part of the Silicon Realization Group at Cadence. Last week (May 20, 2013) Cadence announced the first new product in this space, the Tempus Timing Signoff Solution . Tempus provides up to an order of...
    Posted to Industry Insights (Weblog) by rgoering on Tue, May 28 2013
  • GTC Presentation: Cadence Outlines Comprehensive 20nm Design Flow

    The design and manufacturing challenges of 20nm ICs are formidable, and will not be solved by loose collections of point tools. At the recent Global Technology Conference ( GTC ), Cadence presented its view of 20nm challenges and previewed a comprehensive 20nm design methodology that encompasses custom...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 7 2011
  • Tidbits From TSMC Q209 Earnings Call - 40nm Yield

    Earning calls sure are interesting! Below is an excerpt from the TSMC Q209 call (transcript from seekingalpha). The discussion revolves around the 40nm yield issues and TSMC's ramp to improving the yield. Dr. Liu really hits on a key element of DFM - which is design/layout dependency. Simply put...
    Posted to Silicon Signoff and Verification (Weblog) by wilbur on Fri, Aug 7 2009
  • Assura Foundry Support

    I've been blogging a lot about Assura recently, so I thought I would continue by talking about rule decks. Inside Cadence, we maintain a database that shows which foundries support which process for which products. This means that we can quickly give you an answer if you are considering using a new...
    Posted to Silicon Signoff and Verification (Weblog) by ChrisClee on Mon, Mar 23 2009
  • Getting Good Silicon With More Accurate Timing

    In these difficult economic times, achieving silicon success (functional and meeting specs) within an iteration becomes an even higher priority than before; there might not be a second chance to win that socket or hit that sales window. To that end, there appears to be a heightened interest in variation...
    Posted to Silicon Signoff and Verification (Weblog) by wilbur on Fri, Jan 9 2009
  • DFM in Disguise

    DFM is an overloaded acronym/word. In some design flows, DFM can be found front-and-center and in others, it is just along-for-the-ride. It may be disguised as more rules in a process/rules design manual, or it can be quite explicit in a model-based analysis and optimization flow. But wait, let's...
    Posted to Silicon Signoff and Verification (Weblog) by wilbur on Sat, Jul 12 2008
  • Allow myself...

    In the words of Austin Powers, "Allow myself to..." - well you get the idea. I'm Chris, and I am a Senior Product Marketing Manager for a number of Cadence physical verification, yield analysis and mask design products. I have about 20 years in EDA under my belt. My professional interests...
    Posted to Silicon Signoff and Verification (Weblog) by ChrisClee on Fri, Jul 11 2008
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