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Panelists: What Needs to Happen for 3D-IC TSV Success
It's time to get to work if we want to bring 3D-ICs with through-silicon vias (TSVs) into the semiconductor design mainstream. What ecosystem support is needed in the short term, medium term, and long term to make this new technology successful? That's the question that was put to a panel of...
Posted to
Industry Insights
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rgoering
on Wed, Apr 11 2012
DVCon Panel Debate – “Build or Buy” Emulation and Prototyping?
Emulation and FPGA-based prototyping are becoming increasingly necessary for complex systems-on-chip, but where are these hardware-assisted tools going to come from? Should you invest the resources to build and maintain your own, or purchase a commercially available solution? In either case, what do...
Posted to
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rgoering
on Wed, Mar 7 2012
DVCon Panel: Will Differentiation Through Software Kill Chip Design?
Will systems-on-chip (SoCs) become so expensive to design that people are going to buy chips off the shelf, and differentiate products through software alone? That's one question that was put before a panel of EDA industry experts at the DVCon conference Feb. 29, 2012. Short answer -- no, but we...
Posted to
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by
rgoering
on Thu, Mar 1 2012
Digital and Analog Verification – Round Peg in a Square Hole?
Recently I wrote about a panel discussion that looked at ways of bridging the gap between analog and digital design. This blog post resulted in a lengthy discussion in a LinkedIn group that brought up the topic of verification. One commentator noted that analog and digital designers have very different...
Posted to
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by
rgoering
on Thu, Feb 9 2012
Panelists: Bridging the Gap Between Analog and Digital Design
Analog and digital designers have lived in separate worlds for a long, long time. They use different methodologies and tools, and while digital design is heavily automated, analog design is not. But mixed-signal integration will force this gap to narrow, opening the door to new methodologies and better...
Posted to
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rgoering
on Wed, Feb 1 2012
Synthesis User Panel: Power Dominates Front End Design
What challenges are users facing in front-end IC design these days? According to presenters at a Q&A panel session at a Synthesis Community Event at Cadence Dec. 8, power minimization and optimization are at the top of the list. The panel included three user presenters, an ARM executive, and a Cadence...
Posted to
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rgoering
on Mon, Dec 19 2011
GTC Panel: Getting Best Use From Older IC Process Nodes
Time for a mainstream revolution? That was the title of a lively panel discussion at the Global Technology Conference ( GTC ) Aug. 30. Panelists noted that there's still a lot of activity at 65nm and above. They discussed why this is true, whether mature nodes can be retrofitted with new capabilities...
Posted to
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rgoering
on Mon, Sep 5 2011
Panel Video: Preventing IP Theft in a Global Market
How can semiconductor companies ensure IP integrity in a global marketplace? Are foundries liable if customers use stolen semiconductor IP? Do systems companies really care if their semiconductor IP is stolen? These are some of the questions that emerged at a Design Automation Conference panel in June...
Posted to
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rgoering
on Thu, Aug 4 2011
Hot Topic: Should Separate Teams Handle Analog Verification?
Dedicated verification teams are well established in the digital world, but not in analog/mixed-signal design. Has the time come for separate analog verification teams? I've been following an ongoing debate on this topic in a couple of LinkedIn groups, a debate that followed my recent blog posting...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jul 21 2011
Panel: Is the Cloud the Solution to IC Design Collaboration?
Semiconductor design increasingly requires collaboration by geographically-dispersed design teams, as well as partners and third-party suppliers. Private or public cloud computing may provide a rich environment for this collaboration, but some key questions and challenges remain, according to panelists...
Posted to
Industry Insights
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by
rgoering
on Thu, Jan 20 2011
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