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Palladium

We and Our Competitors Agree (Well, Almost!)

It’s rare in EDA to see competitors agreeing, but an interesting article in EEtimes Europe this week caught my eye, by Lauro Rizzatti the VP Mktg of EVE. Lauro discussed a survey EVE ran during DAC, where they asked customers how they felt about the current state of hardware-assisted verification...

Posted to System Design and Verification (Weblog) by SteveSvoboda on Thu, Nov 12 2009
Keeping Trident Missiles "On Target" With System-Level Verification

Can you think of a more critical application for system-level verification than making ABSOLUTELY CERTAIN a missile carrying nearly 5 Megatons of nuclear payload doesn't have any "bugs"? We've all seen enough James Bond and Superman movies to understand what can happen with "wayward"...

Posted to System Design and Verification (Weblog) by SteveSvoboda on Fri, Oct 23 2009
Virtualization and Simulation Roundtable

A couple of weeks ago I participated in a roundtable discussion led by Peggy Aycinena that has been summarized and posted on edacafe.com . Please have a look if you are interested in Virtual Platform usage for embedded software. One of the things that became clear right away is there are way too many...

Posted to System Design and Verification (Weblog) by jasona on Tue, Oct 13 2009
Q&A Interview: Nimish Modi Describes Front End ‘Paradigm Shift’

Nimish Modi is senior vice president for front end research and development at Cadence. In this interview, he discusses Cadence’s front end strategy in such areas as low power, mixed signal, system development, enterprise verification and predictive design. He also explains why he thinks EDA technology...

Posted to Industry Insights (Weblog) by rgoering on Mon, Aug 10 2009
System D&V at CDNLive! EMEA

CDNLive! EMEA has started today. I arrived here (Munich Germany) from SFO paying $340 for a round trip (record low for trip to Europe). Someone told me today the reason for this was that I have made my reservation at the same time the swine flu news were at their peak and with the decrease in demand...

Posted to System Design and Verification (Weblog) by Ran Avinun on Mon, May 18 2009
The Cadence ESL Machine Keeps Building Momentum!

Last week EDN named Palladium DPA a 2009 EDN Innovation Award Winner , and C-to-Silicon Compiler (a finalist) received two write-ups in www.deepchip.com . One of the write-ups is by Gernot Koch of Micronas who evaluated CtoS last fall. I checked with the CtoS AEs who supported Gernot and his team, and...

Posted to System Design and Verification (Weblog) by SteveSvoboda on Fri, Apr 17 2009
EDN's 19th Annual Innovation Awards

Two of Cadence system D&V products have been selected as the finalists for the EDN innovation award : Palladium DPA (Dynamic Power Analysis) and C-to-Silicon Compiler . I went to the award Dinner this week. In the entrance, I have met Ron Wilson who told me that he believes in the current economic...

Posted to System Design and Verification (Weblog) by Ran Avinun on Fri, Apr 3 2009
Why The Reports of EDA's Demise Are Greatly Exaggerated - Part 2

Part one of this blog looked at what I think are three questionable claims about the EDA industry – that electronics OEMs are going back to internal tool development, that foundries will buy EDA vendors, and that designers aren’t moving to lower process nodes. But whatever the truth of those...

Posted to Industry Insights (Weblog) by rgoering on Thu, Apr 2 2009
Moving Low Power Chip Design up to the System Level

Anybody watching Cadence these past couple years has probably noticed how we're pretty serious about investing in making tools for low-power design. While most of the attention in the EDA industry up to now has been on how to optimize chip power consumption while working at the RTL/gate level, that...

Posted to System Design and Verification (Weblog) by SteveSvoboda on Tue, Mar 24 2009
Emulation vs. FPGA Prototyping

There is a continuous debate about FPGA prototyping vs. emulation. This debate is heating-up with the latest Synopsys acquisitions of FPGA prototyping tools: Synplicity and Chip-It. This debate sometimes reminds me the endless debate between ASIC and FPGA companies. The reality is that there is a market...

Posted to System Design and Verification (Weblog) by Ran Avinun on Thu, Feb 19 2009

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Palladium

We and Our Competitors Agree (Well, Almost!)

Keeping Trident Missiles "On Target" With System-Level Verification

Virtualization and Simulation Roundtable

Q&A Interview: Nimish Modi Describes Front End ‘Paradigm Shift’

System D&V at CDNLive! EMEA

The Cadence ESL Machine Keeps Building Momentum!

EDN's 19th Annual Innovation Awards

Why The Reports of EDA's Demise Are Greatly Exaggerated - Part 2

Moving Low Power Chip Design up to the System Level

Emulation vs. FPGA Prototyping