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Palladium

The Facts: Why Accelerated VIP Is Needed for SoC Verification

On Tuesday May 15 th Cadence announced the expansion of our VIP Catalog to include accelerated VIP (AVIP). You may be wondering why Cadence is investing in accelerated VIP (which runs on an accelerated platform such as the Palladium XP) when we already have the market leading simulation VIP. Good question...

Posted to Functional Verification (Weblog) by PeteHeller on Tue, May 15 2012
In-Circuit Acceleration – A New IC Verification Use Model

Last year Cadence introduced the System Development Suite , a set of four connected hardware/software co-development platforms. Today (May 15, 2012) Cadence is announcing a new release of the System Development Suite that is highlighted by a new verification use model called in-circuit acceleration....

Posted to Industry Insights (Weblog) by rgoering on Tue, May 15 2012
Free DAC Breakfasts: HW/SW Co-Development, 28nm/20nm Challenges

Don't go into the frenzied activity of the Design Automation Conference (DAC) without a good breakfast! Fortunately, you can get a good breakfast and learn a lot from two events sponsored by Cadence Tuesday, June 5 and Wednesday, June 6 at the 49 th DAC in San Francisco. Tuesday June 5 Addressing...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 14 2012
Low Power Design in 2011 and Predictions for 2012

It's that time of year again - winding down towards the end of the year, taking some time with the family, and looking forward to returning refreshed for a new year. So what was the big news for low power in 2011 and what do we have to look forward to in 2012? It's sometimes humbling to look...

Posted to Low Power (Weblog) by Pete Hardee on Thu, Dec 22 2011
Webinar: Easing the Pain of FPGA-Based Prototyping

Nearly every digital system-on-chip, ASIC or ASSP is prototyped in FPGAs, most typically for pre-silicon software development and debugging. The problem is that it can take months to get the prototype up and running with a functionally equivalent design. But there are easier ways to develop FPGA-based...

Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 8 2011
Q&A: Linking Virtual Prototypes to High-Level Synthesis

Virtual prototypes for early software development and high-level synthesis tools for hardware implementation are two important new technologies that are raising the abstraction level in electronic systems design. But these tools are traditionally isolated from one another because they require different...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jun 29 2011
Low Power Design -- Alive and Well at DAC

Low power design was undoubtedly one of the themes of DAC this year -- especially at the Cadence booth. We drew lively interest on the DAC floor with our low power demo station, which was continuously busy especially on the free Monday. We were showing a new demo explaining how advanced low power techniques...

Posted to Low Power (Weblog) by Pete Hardee on Tue, Jun 14 2011
DAC Panel Calls Off “Battle” Between Prototyping and Emulation

A Design Automation Conference (DAC) panel June 8 looked like it was destined for controversy. It was titled, "Software-Hardware Verification Battle: Prototyping vs. Emulation." But that battle didn't happen. Instead, most participants agreed that several types of hardware/software integration...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 14 2011
2011 CDNLive EMEA Highlights and Image Gallery: An EDA360 Spring Festival of Deliverables

Last week teammate Adam Sherer and I had the honor of representing the Incisive functional verification platform at the annual CDNLive for Europe, the Middle East and Africa (EMEA) in Munich, Germany. Among our tasks was to deliver the annual verification roadmap update; support numerous techtorials...

Posted to Functional Verification (Weblog) by jvh3 on Tue, May 10 2011
Why Can’t You Write My Assertions for Me? - Part 3

My last two posts have dealt with various forms of automatic assertion creation and assertion synthesis. There is little doubt that these approaches have significant value, complementing and even replacing some of the assertions written by design and verification engineers. However, I started out this...

Posted to Functional Verification (Weblog) by tomacadence on Wed, May 4 2011

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Palladium

The Facts: Why Accelerated VIP Is Needed for SoC Verification

In-Circuit Acceleration – A New IC Verification Use Model

Free DAC Breakfasts: HW/SW Co-Development, 28nm/20nm Challenges

Low Power Design in 2011 and Predictions for 2012

Webinar: Easing the Pain of FPGA-Based Prototyping

Q&A: Linking Virtual Prototypes to High-Level Synthesis

Low Power Design -- Alive and Well at DAC

DAC Panel Calls Off “Battle” Between Prototyping and Emulation

2011 CDNLive EMEA Highlights and Image Gallery: An EDA360 Spring Festival of Deliverables

Why Can’t You Write My Assertions for Me? - Part 3