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Palladium

DAC 2013: User Perspectives on System-Level Verification

The best way to learn about an emerging technology is to hear from the people who are using it. If you're curious about system-level design and verification, you can do just that at the Cadence System-to-Silicon Verification Breakfast at the Design Automation Conference ( DAC 2013 ) Tuesday, June...

Posted to Industry Insights (Weblog) by rgoering on Wed, May 15 2013
Functional Verification Survey -- Why Gate-Level Simulation is Increasing

In a recent webinar on increasing functional verification performance, the point was made that gate-level simulation usage is increasing. Wait a minute, I thought - haven't we spent the last two decades talking about raising the abstraction level for design and verification? While some IC verification...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 16 2013
Software-Driven Verification – a Hot Topic for 2013?

Many engineers today use C language software running on an embedded processor model to build testbenches for hardware verification. This "software-driven verification" technique is an ad-hoc methodology that often uses home-grown tools. But it's something you may hear more about in 2013...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 3 2013
Bill Beausoleil, 1950s Computer Pioneer, Shapes RTL Emulation Technology Today

An important aspect of any advanced technology -- including the RTL emulation systems used for IC verification - is the expertise that stands behind it. Few can claim more expertise than Bill Beausoleil, an IBM, IEEE and Cadence fellow who designed some of the world's first silicon-based computer...

Posted to Industry Insights (Weblog) by rgoering on Thu, Nov 15 2012
Panelists: Low Power Design Needs System-Level Boost

When low-power design experts get together, much of the conversation turns to the system level. At least that was the case at the recent Low Power Technology Summit held at Cadence Oct. 18, 2012, where audience members questioned panelists about early power estimation, power modeling, and the role of...

Posted to Industry Insights (Weblog) by rgoering on Sun, Oct 28 2012
Si2 Talk: Why System-Level Low Power is Challenging

There's a lot of interest in "system level" low power design -- but what does it really mean? "There a lot of confusion," said Pete Hardee, director of solutions marketing at Cadence, in a presentation at the recent Silicon Integration Initiative ( Si2 ) Conference. "What's...

Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 15 2012
Changing the Game with Processor Based Emulation

I have always been fascinated by game changing moves. Some are more successful than others, but the general principle is always the same - coming with a gun to a knife fight. Two of my favorites are from sports. When I was a young rower, the moving outrigger was a game changer for a while and was a fascinating...

Posted to System Design and Verification (Weblog) by fschirrmeister on Thu, Oct 11 2012
Q&A: Phil Bishop, New Cadence VP, Drives Adoption of System-Level Design

Phil Bishop has come into his new role - Vice President and General Manager of System Level Design at Cadence - at an exciting time. After years of slow growth, technologies such as high-level synthesis and virtual prototyping are seeing adoption and showing results in more and more production environments...

Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 8 2012
Low-Power Design Case Studies: 15 CDNLive! Papers So Far This Year

CDNLive! is back with a bang in 2012, with very strong support from the Cadence user community worldwide. We're three-quarters the way through the events at the time of writing -- you can see the whole program on www.cadence.com at the CDNLive! 2012 Worldwide page. Proceedings are published so far...

Posted to Low Power (Weblog) by Pete Hardee on Mon, Sep 17 2012
User View: Combining Virtual Platforms, Emulation, and Hardware Prototypes

Chuck Cruse, team lead for emulation and FPGA-based prototyping at LSI Corp., wants to build a "deterministic" flow including virtual platforms, emulation, and hardware prototypes. In a recorded audio presentation at the Cadence web site, he describes the challenges he's experienced and...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jul 18 2012

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Palladium

DAC 2013: User Perspectives on System-Level Verification

Functional Verification Survey -- Why Gate-Level Simulation is Increasing

Software-Driven Verification – a Hot Topic for 2013?

Bill Beausoleil, 1950s Computer Pioneer, Shapes RTL Emulation Technology Today

Panelists: Low Power Design Needs System-Level Boost

Si2 Talk: Why System-Level Low Power is Challenging

Changing the Game with Processor Based Emulation

Q&A: Phil Bishop, New Cadence VP, Drives Adoption of System-Level Design

Low-Power Design Case Studies: 15 CDNLive! Papers So Far This Year

User View: Combining Virtual Platforms, Emulation, and Hardware Prototypes