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PSS,noise

  • Jitter from pnoise simulation

    I'm desinnig a Time to digital converter and I would like to simulate the jitter of a driven buffer having a rising time of 350 ps. In my schematic, the buffer is driven by vpulse (ideal CLK @ 2 MHz) and I would like to simulate his output jitter. My setting of pss simulation is as follow: Beat frequency...
    Posted to RF Design (Forum) by moez on Fri, Mar 9 2012
  • Blog post on simulator analysis & when to use what

    This free article isn't all that relevant for experienced designers, but for the novice, it is helpful: http://www.circuitdesign.info/blog/2008/11/circuit-simulator-analyses/ (Full disclosure: I wrote it.)
    Posted to RF Design (Forum) by PoojanWagh on Fri, Nov 21 2008
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