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PSO,power shutoff

  • New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF

    On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release . Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE 1801/UPF are the key capabilities in the release...
    Posted to Low Power (Weblog) by Adam Sherilog on Tue, May 7 2013
  • Low-Power Technology Summit Proceedings Now Available

    On October 18, 2012 Cadence held a Low-Power Technology Summit at our San Jose, California headquarters. Experts from Cadence and other leading companies presented the latest low-power design methodologies. Well, it took us a while but you can now view the material via the Low-Power Technology Summit...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, Dec 5 2012
  • Your First Low-power Verification Project - Webinar

    So your team just specified its first design with power management circuits. The designers are telling you, its just a few power shut-off domains defined by CPF or UPF. The verification should be easy-peasy right? Wrong. Each domain has complete controls, isolation, and retention. As a verification engineer...
    Posted to Low Power (Weblog) by Adam Sherilog on Thu, Oct 11 2012
  • What’s Cool for Low-Power at DAC?

    Low-power design promises to be a key theme of the Design Automation Conference once again! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), if you need to cover design, implementation and verification of this important subject, there's a lot to choose from at Cadence's...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, May 30 2012
  • Low-Power Design? Brian Bailey Gets It

    Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of editorials, opinion pieces and contributed articles on the subject of low power design. As he...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, May 2 2012
  • User View: “Multi-Mode” Synthesis Approach Includes Power Optimization

    Logic synthesis is an indispensible IC design tool, but its value has a lot to do with how it's used. At a recent Synthesis Community Event at Cadence Dec. 8, Laszlo Borbely-Bartis, staff design engineer at Micron, described a concurrent multi-mode and low-power optimization synthesis flow using...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 5 2012
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