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PSO,low-power design

  • New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF

    On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release . Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE 1801/UPF are the key capabilities in the release...
    Posted to Low Power (Weblog) by Adam Sherilog on Tue, May 7 2013
  • Low-Power Technology Summit Proceedings Now Available

    On October 18, 2012 Cadence held a Low-Power Technology Summit at our San Jose, California headquarters. Experts from Cadence and other leading companies presented the latest low-power design methodologies. Well, it took us a while but you can now view the material via the Low-Power Technology Summit...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, Dec 5 2012
  • Perspective on Power: 2012 Survey Predicts 2013 as the Year of DVFS

    The recent Low-Power Technology Summit held at Cadence headquarters in San Jose gave us a great opportunity to take the pulse of low-power design by surveying the attendees. Some of the data we got was expected, but there were a couple of surprises. First, some of the expected stuff. We'd noticed...
    Posted to Low Power (Weblog) by Pete Hardee on Thu, Nov 29 2012
  • What’s Cool for Low-Power at DAC?

    Low-power design promises to be a key theme of the Design Automation Conference once again! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), if you need to cover design, implementation and verification of this important subject, there's a lot to choose from at Cadence's...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, May 30 2012
  • Low-Power Design? Brian Bailey Gets It

    Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of editorials, opinion pieces and contributed articles on the subject of low power design. As he...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, May 2 2012
  • Does Substrate Biasing Have a Future?

    At Cadence, we often get asked about various low-power design techniques: how well they work, what are the implementation and verification issues associated with them, and how effective they are at various process nodes. As a general trend we see aggressive power reduction techniques being adopted more...
    Posted to Low Power (Weblog) by Pete Hardee on Mon, Feb 6 2012
  • GUC User Presentation at DAC: How to Do Low Power Design

    Power was clearly a hot topic at the recent Design Automation Conference (DAC). Many companies demonstrated their unique tool capabilities to address power issues at different abstraction levels. However, we saw very few presentations that offered a user perspective on how they do low power designs and...
    Posted to Low Power (Weblog) by QiWang on Mon, Jun 13 2011
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