Home > Community > Tags > PSO
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

PSO

  • Digital Centric Mixed-Signal Dynamic Power Verification – Bringing It All Together

    This is the final posting in a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will talk about concepts behind digital-centric mixed-signal verification (DMSV). My previous blogs covered some of the following topics: 1. Basics of...
    Posted to Low Power (Weblog) by Neyaz on Tue, Oct 19 2010
  • Analog Coverage Metrics in Mixed-Signal Simulations

    This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will cover metrics collection from analog circuits during mixed-signal simulation. My previous blogs covered some of the following topics: 1. Basics of dynamic...
    Posted to Low Power (Weblog) by Neyaz on Tue, Oct 5 2010
  • Error Detection for Controlled Voltage Sources and Voltage Scaling

    This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will cover error detection. My previous blogs covered some of the following topics: 1. Basics of dynamic power management 2. Very brief introduction to RNM...
    Posted to Low Power (Weblog) by Neyaz on Tue, Sep 21 2010
  • 5 Tips to Help You Finish Your Low Power Design Tapeout On Time

    So you're about to start your first low power design. Or second, third, or fourth. As with many tapeouts, you know that with today's tight market windows, most likely the project will go off with a sprinting start (architectural planning), followed by an endurance test (designing and implementing...
    Posted to Low Power (Weblog) by Design4Life on Fri, Aug 27 2010
  • Dynamic Power Management – Closed Loop Voltage Scaling

    This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I'll discuss open-loop and closed-loop voltage scaling. In previous blogs, I covered some of the following topics: Basics of dynamic power management Very...
    Posted to Low Power (Weblog) by Neyaz on Tue, Aug 24 2010
  • Power Analysis: When Accurate Isn’t Accurate At All

    The notion that your ability to analyze power dissipation more accurately as your design proceeds down the levels of abstraction from system-level, to RTL, and to gate-level and transistor-level netlist has existed unchallenged for too long. Well, would I be tilting at windmills to challenge it? I could...
    Posted to Low Power (Weblog) by Pete Hardee on Fri, Aug 20 2010
  • A Call For Power-Aware IP Models

    Power intent formats exist to express the design's low power techniques separately from the design's functional description. This promotes portability of the design across different power schemes. So why are most commercial IP providers forced to bury this critical information deep in gate-level...
    Posted to Low Power (Weblog) by Pete Hardee on Tue, Aug 3 2010
  • User Interview: Forging A Multi-Mode Synthesis Flow

    Traditional synthesis flows aren’t keeping up with IC complexity and low-power demands, according to Laszlo Borbely, design engineer at Micron Technology . At the recent CDNLive! Silicon Valley , Borbely discussed a new flow that uses concurrent multi-mode synthesis and low-power optimization based...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 9 2009
  • Cadence and Very Cool Stuff

    One of the very cool things about my job is that I get to see all kinds of new stuff early. I’m privileged to be involved in technology roll outs, and so get to be involved in early discussions with R&D, Product Engineering, and Marketing. And, I gotta tell you, there is very cool stuff coming...
    Posted to Digital Implementation (Weblog) by Rich Owen on Tue, Nov 3 2009
  • When Do You Know You've Saved Enough Power?

    This guest post is by David Weir, Lead Design Engineer at Cadence. His paper, "When do you know you've saved enough power?" was voted best-in-track for Logic Design at CDNLive! 2008 Silicon Valley. In this paper we set out to show how designers can measure and explore the impact of implementing...
    Posted to Logic Design (Weblog) by Team FED on Thu, Apr 2 2009
Page 2 of 3 (22 items) < Previous 1 2 3 Next >