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PSL

DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!

In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can...

Posted to Industry Insights (Weblog) by rgoering on Tue, May 1 2012
question about PSL

Hi, all: I want to do assertion check in a "for" loop, and I want to do assertion check in every loop(totally 10 times in my file), but it seems that the assertion check only done once, and at the very beginning of the file instead of after going into the loop. ncsim shows "ncsim: *E,...

Posted to Functional Verification (Forum) by jxker on Fri, Apr 6 2012
Video: PSL and SVA for SPICE – Yes, Assertion Based Verification (ABV) for Analog Behavior!

In this video, Senior Architect in Virtuoso R&D Don O'Riordan shares some background information on his DVCon 2012 paper, "PSL/SVA Assertions In SPICE." Wait, aren't Property Specification Language (PSL) and SystemVerilog Assertions (SVA) digital assertion-based verification (ABV...

Posted to Functional Verification (Weblog) by TeamVerify on Mon, Mar 26 2012
Video Killed The Reference Manual Star

[Preface: recall the melody of the Buggles' 1979 hit " Video Killed the Radio Star " as you read the following] Q: What is your favorite pastime? A: Reading reference manuals! No? Really? OK -- with all due respect to our Tech Pubs team, virtually no one wants to sit down and read reference...

Posted to Functional Verification (Weblog) by TeamVerify on Thu, Jan 26 2012
Webinar Report: Power-Aware Mixed-Signal Verification

Most of the discussion about low-power design techniques has focused on digital circuits. However, nearly all systems-on-chip (SoCs) are mixed-signal, and the way in which analog and digital circuitry interact has a huge impact on overall power consumption. Thus, low power (or "power aware"...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 25 2012
Webinar Report – New Approaches to Mixed-Signal Verification and Assertions

Nearly all systems-on-chip (SoCs) are mixed-signal, and as complexity grows, new verification techniques are needed. No longer is it sufficient to use traditional analog and digital simulation in isolation - instead, information must flow freely between analog and digital domains to allow a true mixed...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 19 2012
Early Holiday Present: Sudoku Solver Using Incisive Enterprise Verifier (IEV) and Assertion-Driven Simulation (ADS)

Allow me to interrupt the excellent "Meet R&D" series to share a small holiday present. On the Functional Verification Shared Code Forum I've just posted a ZIP file with Sudoku solver code for Incisive Enterprise Verifier (IEV) . The file is at http://www.cadence.com/community/forums...

Posted to Functional Verification (Weblog) by TeamVerify on Tue, Dec 13 2011
Sudoku solver using Incisive Enterprise Verifier (IEV) and Assertion-Driven Simulation (ADS)

Just in time for the holidays, inside the posted tar ball is some code to solve 9x9 Sudoku puzzles with the Assertion-Driven Simulation (ADS) capability of Incisive Enterprise Verifier (IEV). Enjoy! Joerg Mueller Solutions Engineer for Team Verify

Posted to Functional Verification Shared Code (Forum) by TeamVerify on Tue, Dec 13 2011
Formal Verification with Asynchronous Clocks

Many designs have multiple independent clock inputs with different frequency specifications and/or different frequency ranges. In simulation based environments we see regressions run with randomly varying clock phase timing parameters to cover the many possible combinations. A simple Verilog example...

Posted to Functional Verification (Weblog) by TeamVerify on Thu, Oct 13 2011
M/S Technology on Tour Blog – Model Validation and Assertion Based Verification

In February 2011, I had the opportunity to meet a group of analog and mixed-signal design and verification engineers in Boston, Austin and Irvine as part of the Cadence Mixed-Signal Tech-on-Tour program . This was a revealing experience for me in many ways. Having been intimately involved with the AMS...

Posted to Mixed-Signal Design (Weblog) by PrabalB on Tue, Jun 28 2011

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