Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
More Products
OrCAD Products
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
IP Alliances
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Quicklinks
All Blogs
All Forums
Community Search
CDN
Live!
User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> PDK
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
All Blog Categories
Popular Tags
Allegro
ARM
Custom IC Design
DAC
Digital Implementation
e
EDA360
encounter
ESL
Functional Verification
Incisive
industry insights
Logic Design
Low power
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
SystemVerilog
TLM
UVM
verification
Virtuoso
Browse All Tags
Share
Email
Social Web
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
PDK
90nm
ADE
ADE "Model Setup"
ADE ADEXL
ADE XL
ADEGXL
Allegro
Analog
ARM
av_extracted
backend implementation
Cadence
Cadence model spice
CDF Parameters
CDNlive
CDNLive!
Coventor
custom
custom design
custom design technology
Custom IC
Custom IC Design
design chain
DRC
ecosystem
Equation
error
Feuillette
GTE
IBM
IC 6.1
IC Packaging & SiP design
IC6.1.4
IC610
IDMs
Industry Insights
Industry Insights: ARM
Interoperability
IPL
Layout
Lisp
MEMS
Mentor
National Semiconductor
OpenAccess
OpenPDK
PAS
PCell
PCells
PDKs
Process Design Kit
PVS
Python
Si2
Simulator
SKILL
spectre
SPICE
stmicroelectronics
Techfile
TMSC
Virtuoso
Virtuoso Analog Design Environment
webinar
how to get FAB pdks
Greetings! Can anyone guide me how exactly can we (a University IC Design Lab) get a FAB PDK for our projects? Is the NCSU CDK a substitute for the actual FAB PDKs? Can the GDS II file of a project using NCSU CDK sent to the FAB for fabrication? If so, what is the difference between the FAB's PDK...
Posted to
Digital Implementation
(Forum)
by
Mashhood
on Wed, Jun 22 2011
Aging simulation with RelXpert and Eldo
Hello everyone I would like to simulate the aging behavior on circuit-level of the circuits built by bulk-Si CMOS technology. I know that there is a tool named “RelXpert” (combined with UltraSim) in Analog Design Environment (ADE) of Cadence Virtuoso can be used for aging (NBTI and HCI) simulation...
Posted to
Custom IC Design
(Forum)
by
SilentHunter
on Sun, May 15 2011
Webinar: Cadence, Mentor Find Common Ground on PDK Standards
Representatives of Cadence and Mentor Graphics don't often appear in the same webinar, but there's a new development in the industry that was important enough to bring these two EDA vendors together Dec. 7. That development is OpenPDK , a process design kit standardization effort launched by...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Dec 12 2010
User Presentation: Automatically Generated SKILL PCells Speed PDK Development
Process design kit (PDK) developers have been using the SKILL language to code PCells (parameterized cells) for over two decades. SKILL is a flexible, extensible, Lisp-based language that can do just about anything a programmer wants to do. But is there an easier way to create PCells? Yes, according...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 1 2010
The Case For SKILL PCells and PDKs
Controversy is continuing over the use of Cadence SKILL language PCells versus "interoperable" parameterized cells written in Python. What's getting lost in this discussion is an important question: What are the advantages of SKILL for process design kit (PDK) development and analog/custom...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Sep 16 2010
Ten Things You (Probably) Didn’t Know About SKILL
The Cadence SKILL language has received some press lately as part of an ongoing debate over process design kit (PDK) standards. This post isn't about that. Rather, it's about the story behind SKILL, a venerable language that's far more than just a format for describing PCells in custom IC...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Aug 9 2010
Seven Requirements For An Open PDK Standard
My May 13 blog discussed the significance of the Silicon Integration Initiative (Si2) OpenPDK Coalition , which is seeking to define an open standard that will allow foundries to create a single process design kit (PDK) representation that can be translated into different input formats. What is necessary...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Fri, May 14 2010
What OpenPDK Is And Why It’s Important
Since process development kits (PDKs) are necessary for all IC design, a major change in the way foundry PDKs are provided is significant news. Such change may be forthcoming from the Silicon Integration Initiative (Si2) OpenPDK Coalition , which announced 10 founding members, including Cadence, May...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, May 13 2010
Bringing MEMS Design To The Mainstream
Micro-electrical mechanical systems ( MEMS ) have been around for years, and have found their way into high-volume applications such as automobile air bag controllers, GPS systems, and inkjet print heads. But MEMS devices such as accelerometers, gyroscopes, RF switches and pressure sensors are not as...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 15 2010
Q&A: A Cadence View Of ‘Interoperable’ PCells
If you’re involved in analog or custom IC design, you’ve no doubt read about “interoperable” parameterized layout cells (PCells) and process design kits (PDKs). What you probably haven’t heard is a Cadence viewpoint about these developments. The following Q&A interview...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 13 2010
Page 1 of 2 (17 items) 1
2
Next >