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PCI Express
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Cadence Cosmic Circuits Acquisition – Analog/Mixed Signal IP for Advanced Node SoCs
Last week (Feb. 7, 2013) Cadence announced an agreement to acquire Cosmic Circuits Private Limited, a leading provider of analog/mixed-signal IP based in Bangalore, India. Here's some background on this relatively young, fast-growing company, and how its offerings fit into the growing Cadence design...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 11 2013
Martin Lund Keynote: Time to Rethink Semiconductor IP “Reuse”
People have been talking about semiconductor IP "reuse" for many years, but is IP really reusable as is? It's increasingly unlikely, according to Martin Lund (right), senior vice president of the SoC Realization Group at Cadence. In a recent keynote speech, Lund said that continuous changes...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 19 2012
Allegro 16.6: Easing PCB Design for Multi-Gigabit/Second Signals
Got a few picoseconds to spare? If you're a PCB designer working with a multi-Gbit/second serial link interface such as PCI Express 3.0 or a DDR memory interface, maybe not. Two new features in the Cadence Allegro 16.6 PCB design solution - announced today (Sept. 25, 2012) at PCB West - aim to help...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Sep 25 2012
Panel: Signal Integrity Solutions for High Data Rate Interfaces
Serial link and DDR memory interfaces are well into Gbits/second territory, making it possible to design a new generation of high-performance devices. But these new interfaces can also greatly increase signal integrity challenges. At an August 28 EDN-hosted webinar panel , experts provided a wealth of...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Sep 4 2012
Flash Memory Panelists Challenge Conventional Thinking About NAND and SSDs
What you think you know about flash memory may be wrong, according to a provocative panel discussion at the Flash Memory Summit Aug. 23, 2012. Panelists were asked to come up with the "top ten things you need to know about flash memory today," and while not all had ten items, all had some original...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Aug 26 2012
Cadence Video Demonstrates PCIe Gen3 IP Silicon Performance
It is not often that an IP provider gets to showcase their IP performance in a real product demo. Those laurels usually end up going to the end product that uses the IP. But a recent Cadence video features our PCI Express (PCIe) Gen 3 core running flawlessly in silicon in a real system. We thought we...
Posted to
Design IP
(Weblog)
by
ashwinmatta
on Mon, Aug 6 2012
Semico Conference: “System Driven” Semiconductor IP Leads to IP Subsystems
A "new breed" of semiconductor intellectual property (IP) is required for the next stage of evolution in the IP ecosystem, according to a keynote speech by Vishal Kapoor (right) of Cadence at the Semico Impact Conference May 16, 2012. This new type of IP will be "system driven," and...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, May 17 2012
How IP Subsystem Will Speed NVM Express (NVMe) Adoption
Non-Volatile Memory Express (NVM Express or NVMe) is an emerging protocol standard for accessing solid state drives (SSDs) over PCI Express (PCIe) links. It would thus make sense, if you're designing an SoC that has an SSD interface, to cobble together a subsystem that includes an NVMe controller...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 15 2012
Free PCB Signal Integrity Education from Robert Hanson Continues at Cadence in Austin
Over fifty PCB enthusiasts ascended upon the Cadence campus in Austin, Texas last month where they were greeted by world renowned signal integrity educator Robert Hanson. Robert spent two full days taking them from the basics of transmission line theory all the way through the challenging aspects of...
Posted to
PCB Design
(Weblog)
by
TeamAllegro
on Tue, May 8 2012
How TripleCheck IP Validator Eases Use of Verification IP (VIP)
Reusable, commercial verification IP (VIP) has greatly eased the functional verification task for complex interface protocols. However, verification engineers still have a significant amount of manual work to perform. Cadence this week is addressing this problem by announcing the TripleCheck IP Validator...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Apr 30 2012
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