Home > Community > Tags > PCB layout/package
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

PCB layout,package

  • homogenous symbols

    Hi, I am using Homogenous -'parts per package' symbol on my design. i get a netlisting error if i dont connect the power pins present on all the parts. ( for eg. for a HEX inverter IC with 6 parts, the power (#14) & GND (#7) pins are present on all the parts. ) is there a way to avoid connecting...
    Posted to PCB Design (Forum) by marysmita on Thu, Jul 4 2013
  • 16.5 New footprint from Package Designer to PCB Editor?

    Hello, I am a new 16.5 user. I designed some footprints in package designer as per the tutorials. I saved them in a folder as .psm and .dra parts. However when I go to create a netlist in Capture, or even to simply manually place the parts in PCB Editor neither I nor the software can find them. In PCB...
    Posted to PCB Design (Forum) by Grue42 on Tue, Oct 16 2012
  • Allegro 16.6: Easing PCB Design for Multi-Gigabit/Second Signals

    Got a few picoseconds to spare? If you're a PCB designer working with a multi-Gbit/second serial link interface such as PCI Express 3.0 or a DDR memory interface, maybe not. Two new features in the Cadence Allegro 16.6 PCB design solution - announced today (Sept. 25, 2012) at PCB West - aim to help...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Sep 25 2012
Page 1 of 1 (3 items)