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PCB layout,PCB design

  • Great Opportunities in EDA, ARP, Place and Route, Layout, Management and Logic Design

    I have been contacted with some outstanding new opportunities inside a large corporation that has a big presence in Silicon Valley, CA and Austin, TX. We are looking primarily for experts in ECAD, EDA, Place and Route, Layout, etc. There are approximately 30 positions open, which is a welcome sign of...
    Posted to Jobs (Forum) by epeefencer on Tue, Feb 11 2014
  • Seagate, Shrewsbury MA, Full Time, CAD Designer PCB Layout - Allegro

    Seagate Technology is seeking an experienced Sr. Electrical CAD Designer for Printed Circuit Board (PCB) Layout to join our Solid State Drives Development team. The candidate will work in a world class design center with highly experienced individuals focused on cutting-edge storage technologies. This...
    Posted to Jobs (Forum) by VickeyT on Thu, Nov 14 2013
  • design tools

    what is the difference between port and off-page connector in orcad? please repli 4 my ques...
    Posted to PCB Design (Forum) by vvlak on Sun, Mar 3 2013
  • Multiple SRAMs 1 data bus

    I am creating a pcb with multiple srams connected to an FPGA on 1 data bus. I intend to clock the srams and the fpga at 150 MHz. I am concerned about what issues will arise when connecting mutliple srams to the same data bus (only 1 sram will have its output enabled at a time). For example should I worry...
    Posted to PCB Design (Forum) by neseroth on Fri, Jan 25 2013
  • Design Entry HDL Training

    Hi there! Is there any training offering for Design Entry HDL here in Philippines? Please let me know. Thanks.
    Posted to PCB Design (Forum) by comet on Thu, Jan 24 2013
  • PCB Design and Layout

    Hi all, I am really stuck in the following problem, please help me... When we import a circuit drawn in the ORCAD Schematic into the ORCAD Layout with necessary Netlist, does the connection integrity (even in cases where the interconnecting lines as seen in the layout as soon as they are imported) is...
    Posted to PCB Design (Forum) by Wonderman on Tue, Nov 20 2012
  • Allegro 16.6: Easing PCB Design for Multi-Gigabit/Second Signals

    Got a few picoseconds to spare? If you're a PCB designer working with a multi-Gbit/second serial link interface such as PCI Express 3.0 or a DDR memory interface, maybe not. Two new features in the Cadence Allegro 16.6 PCB design solution - announced today (Sept. 25, 2012) at PCB West - aim to help...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Sep 25 2012
  • Edit-Copy generates DRC "Line to thru pin spacing" errors

    Am I missing something on how to make an array of boards? I chose Edit - Copy, provided the spacing I wanted for the boards, the number of boards to create, then clicked "All On" for the "Find" filter. I drew a box around the board, picked my origin, and then placed the new array...
    Posted to PCB Design (Forum) by admin on Thu, Aug 30 2012
  • Experienced OrCad 15.7 user available

    I am an OrCad 15.7 Capture CIS and PCB Layout user with 20+ years experience available for evening work a few nights a week. I also have experience of EasyPC and other systems. I have valid licences for EasyPC version13 to latest and OrCad. If you require help, they I can be contacted via an email form...
    Posted to Jobs (Forum) by tmd63 on Mon, Jul 23 2012
  • Greeting to all guys here

    Hello, guys, it is my first time to know you here. This is Jack from SOPPCB TECHNOLOGY in Shenzhen, China, we are a factory to make PCB fabrication and assembly for nearly 10 years. If any one here need to make PCB boards, pls contact me. Jack soppcbtech at gmail dot com SOPPCB
    Posted to PCB Design (Forum) by SOPPCB on Fri, Feb 17 2012
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