Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> PCB Layout and routing
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
PCB Layout and routing
"PCB design"
16.2
16.3
16.5
16.6
advanced package designer
Allegro
Allegro 16.3
Allegro 16.5
Allegro 16.6
Allegro GUI
Allegro PCb
Allegro PCB Design XL
Allegro PCB Editor
Allegro PCB SI
Allegro System Architect (ASA)
APD
ASA
Capture CIS
CDNLive
circuit design
ConceptHDL
Constraint Manager
Constraint-driven PCB Design flow
constraints
DDR2
DDR3
DEHDL
design
Design Entry
Design Entry HDL
diff pairs
Differential Pair Support
differential pairs
DRC
Drill holes
ECSets
embedded components
export
Footprint
FPGA
FPGA System Planner
FPGA-PCB Co-Design
Front-end PCB design
FSP
Gerber
global route
GRE
Grzenia
HDI
High Speed
High-Density Interconnect
IC Packaging
IC Packaging and SiP Design
inset vias
interconnects
IPC standards
jumper board
layer stacks
layers
layout
Librarians
Library
Library and design data management
microvia
netlist files
Online Support
Orcad
OrCAD Capture
orcad Capture allegro netlist 16.3 16.2
Orcad Layout
OrCAD PCB Editor
PCB
PCB Capture
PCB design
PCB Designer
pcb editor
PCB layout
pcb layoutyout
PCB manufacture
PCB SI
PCB Signal and power integrity
PCB Signal integrity
placement edit
RF
routing
Schematic
shape
SI
SPB
SPB 16.3
SPB16.01
SPB16.2
SPB16.3
SPB16.5
Specctra
via
via rules
vias
XAUI
one design spanning multiple boards
Hi. We're using Allegro PCB Design XL 16.2 to do our layouts, and I am in the process of splitting a design from one board into two boards. Is there a way to do this, and still keep things within the same .dsn file? For example, consider the following layout of an imaginary design called whatever...
Posted to
PCB Design
(Forum)
by
mpfleger
on Tue, Mar 2 2010
Shape to Route Keepin Spacing
OrCAD PCB Designer v16.2 I am getting the following DRC error, regarding an auto-generated shape (ground or power pours). I get it on multiple layers with multiple pours: Constraint Name = Shape to Route Keepin Spacing Required Value = 0 MIL Actual Value = 0 MIL Constraint Source = DEFAULT Constraint...
Posted to
PCB Design
(Forum)
by
melview1
on Tue, Feb 23 2010
Reviewing the Board files
Hi All, I have been assigned with a new job of reviewing Board files. Can some one please tell me what and all has to be reviewed form Layout ,Gerber and Design poiint of View. PLease Guide me. Regards, Kingshark
Posted to
PCB Design
(Forum)
by
kingshar
on Mon, Feb 1 2010
Automatic Routing Update From Constraint Change
Hi Folks, I am in Allegro 16.2 and I have had to create a new Physical Constraint Set (PCS/Physical CSet) for which I want several nets and DPr(differential pair)/nets ro reference. I have changed the values for Line Width,Neck etc and they have saved. Is there a way to have these changes: 1) populate...
Posted to
PCB Design
(Forum)
by
Thomas M
on Tue, Dec 15 2009
Find the 90 degree routing
hi experts, is there any methods or skill to check the 90 degree or the short length bend(eg. less than 3W)routing in layout?
Posted to
PCB Design
(Forum)
by
tonychen
on Sun, Sep 27 2009
Power Issues? Manage Your IR Drop The "Advanced" Way
Just added to the Cadence Resource Library for Allegro PCB SI is a whitepaper written by Advanced Layout Solutions. In this post, Chris Halford discusses how his company works to ensure the PCBs they design meet requirments for voltage and temperature stability. As Chris mentions, the challenge of managing...
Posted to
PCB Design
(Weblog)
by
Maxwell86
on Tue, Aug 11 2009
Re: Orcad Layout 15.7 -SST -file missing in post processing output
Was your OrCAD "Layout" missing "SST" question ever answered for you? Are you having any other problems? You can contact me at: midnight_blue_designs@yahoo.com and I'll try and help you out. JBW
Posted to
PCB Design
(Forum)
by
Midnight Blue
on Tue, Jun 23 2009
Complemented training course for displaced workers?
I learned that Mentor offers free training course for displaced (unemployed) workers, who are laid off less than 6 months. Does Cadence also offer such program for Cadence users to renew/refresh on different tools? Thanks in advance.
Posted to
PCB Design
(Forum)
by
VTAA
on Wed, Jun 17 2009
How to export 3D model from allegro pcb editor 16.01?
Hi, I am using Allegro PCB Editor 16.01. My customer asking 3d model for the paricular board....But i dont know ,what file i have to export.Plese help me. Thanks In Advancce. Regards, lingam
Posted to
PCB Design
(Forum)
by
Lingam
on Mon, Jun 1 2009
Can batch file be used in Command line in PCB editor?
for example, a batch file for highlight several nets and component. can batch file be execute in command line? and which command is for executing batch file? Thank you and Regards,
Posted to
PCB Design
(Forum)
by
2win
on Sun, May 24 2009
Page 9 of 12 (119 items)
« First
...
< Previous
7
8
9
10
11
Next >
...
Last »