Home > Community > Tags > PCB Layout and routing
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

PCB Layout and routing

  • What's Good About Allegro Router and Via Changes? SPB16.3 Has a Few New Enhancements!

    This week, I’ll be closing discussions on the new SPB16.3 Allegro PCB Router improvements. The focus is on several enhancements for via support. The Use_Via Rule Many times you need to restrict the usage of specific vias in a region. Allegro PCB Router has been enhanced in the SPB16.3 release to...
    Posted to PCB Design (Weblog) by Jerry GenPart on Wed, Oct 20 2010
  • What's Good About Allegro PCB Editor Customizable Datatips? Look to SPB16.3 and See!

    In pre-select mode Allegro displays a datatip that provides information about the element that is being hovered over. The TAB key can be used to cycle through the string of elements such as symbol, pin, and net, resulting in a new display of the datatip. In the SPB16.3 release of Allegro PCB Editor ...
    Posted to PCB Design (Weblog) by Jerry GenPart on Wed, Oct 13 2010
  • PCB autorouter(spectraa) not converging

    Hi, I am making my first pcb with a xilinx fpga device(256 pin BGA package).I am simply connecting the all I/O's to 4 standard 40 pin connectors.Are padstacks necessary for PCB routing??.I have drawn the schematic in Capture imported it to Layout_Plus and autorouted it. But after 3 hours of autorouting...
    Posted to PCB Design (Forum) by bennyn1 on Thu, Sep 2 2010
  • Flexi-Rigid contacts / place component on inner layer?

    My current flexi-rigid design: Head section (rigid L1-6), Neck section (flexible L2-5), Body section (rigid L1-6), Tail section (flexible L4-5) with exposed contacts (J1) on L4 for insertion into a ZIF socket. I've created J1 as a component but can't place it on an inner layer i.e. L4. Can components...
    Posted to PCB Design (Forum) by AlanSpectrum on Mon, Aug 16 2010
  • Pad Seed Points

    Using OrCAD PCB Designer v16.3.S009 I would like to know how to control the copper seed point on a particular symbol, but not the whole design. I have a shield over a part that has 4 pads that are all GND. This part is on the top layer which has a GND copper pour dynamic shape. When I smooth the shapes...
    Posted to PCB Design (Forum) by melview1 on Wed, Aug 4 2010
  • What's Good About Allegro GRE Bundle Editing? SPB16.3 Has Many New Enhancements!

    The Allegro Global Route Environment (GRE) has expanded its capabilities in the area of bundled editing in the SPB16.3 release. It’s now easier to copy, move, and split bundles. Copy Flow lets you copy the flow path from one bundle to another. Its primary goal is to allow faster creation of the...
    Posted to PCB Design (Weblog) by Jerry GenPart on Wed, Jul 28 2010
  • Differential Pairs

    Using OrCAD PCB Designer v16.3.S009 Can anyone help me on how to route a differential pair to be the same length and same separation during the whole route? I'm sure there's some properties or modes I am missing that makes this easier than doing it manually. Thanks. --Mark
    Posted to PCB Design (Forum) by melview1 on Thu, Jul 22 2010
  • Antenna Trace Relief

    Using Allegro OrCAD PCB Designer v16.3.S009 I have a 2.4GHz impedance controlled antenna trace that has a ground pour around it. I would like to pull back the ground pour at least 30 mils from this antenna trace. Is there a property or something in the net or trace that I can set such that it will automatically...
    Posted to PCB Design (Forum) by melview1 on Thu, Jul 22 2010
  • Cadence 14.0 : DRC error Line to SMD Pin Spacing

    Hello, I route a board on Cadence 14.0 and have an unknown problem. Each time I try to connect 2 pins of a same net, I have 2 DRC errors : Line to SMD Pin Spacing. More over, when I connect these 2 pins, it is not automaticaly directed to the center of the second pin. Is thre anyone who can help me ...
    Posted to PCB Design (Forum) by romaric on Wed, Jul 7 2010
  • What's Good About Via DRCs In Allegro Constraint Manager? It's In SPB16.3!

    Current design technologies require extremely tight matching requirements right down to the overall net topologies to ensure that any deviations in propagation delays are minimized. As a result, design guidelines call for matching the number of vias for a group of signals. The prior releases of Constraint...
    Posted to PCB Design (Weblog) by Jerry GenPart on Fri, Jul 2 2010
Page 9 of 14 (133 items) « First ... < Previous 7 8 9 10 11 Next > ... Last »