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PCB Signal and power integrity

  • Re: Sigwave - waveform with suffix "i"

    I found this explanation: "The waveforms are identified by the point at which the waveform is measured. For example, the waveform named B U1 62 is measured at the pin of the device, while the waveform named B U1 62i is measured prior to the pin of the device. This yields a waveform that includes...
    Posted to PCB Design (Forum) by Juniper on Wed, Sep 15 2010
  • Sigwave - waveform with suffix "i"

    I'm getting two waveforms for the receiver, one with suffix "i" in the nodename and another without. What does suffix "i" mean and what is the difference between the two waveforms? thanks
    Posted to PCB Design (Forum) by Juniper on Tue, Sep 14 2010
  • What's Good About The PCB SI Model Editor? See For Yourself In The SPB16.3 Release!

    With the SPB16.3 release of PCB SI , the Model Editor has been added to allow you to view, update, and check the syntax and data integrity for various models. The first release of the model editor contains simple functions. More utilities, tools, and features will be added in future releases. The Model...
    Posted to PCB Design (Weblog) by Jerry GenPart on Wed, Aug 4 2010
  • Antenna Trace Relief

    Using Allegro OrCAD PCB Designer v16.3.S009 I have a 2.4GHz impedance controlled antenna trace that has a ground pour around it. I would like to pull back the ground pour at least 30 mils from this antenna trace. Is there a property or something in the net or trace that I can set such that it will automatically...
    Posted to PCB Design (Forum) by melview1 on Thu, Jul 22 2010
  • EMC & SI

    Asyou know well, for improving SI and EMC, it is better to use strip line instead of microstrip. However, to use Strip-line, basically I need to place a via for each signal. I must make IC package much bigger. Assuming low cost PCB 4-6 Layer, 18-mil via and 4/4mil trace, controller BGA package must be...
    Posted to PCB Design (Forum) by System Archite on Wed, Jul 21 2010
  • Regarding Xnet properties getting lost

    Hi, I am currently using 15.7 Allegro PCB Design XL. I have assigned Models to components to assign XNET properties. Whenever iam importing the latest netlist the Xnet properties are getting lost. Our schematic engineers are using Mentor Dx Designer to generate netlist in .tel format. Every time I import...
    Posted to PCB Design (Forum) by kingshar on Wed, May 26 2010
  • DDR3 Timing issues? Watch the Allegro PCB SI / TimingDesigner Webinar!

    Last year, TimingDesigner improved the interface to PCB SI and many of our joint customers have taken advantage of performing static timing analysis on their fully routed boards using the two tools together. However, DDR3 adds a whole ’nother level of complexity with its faster speeds, lower voltages...
    Posted to PCB Design (Weblog) by TeamAllegro on Mon, May 17 2010
  • What's Good About Simplifying the Use of Third-Party SI Models? It's in SPB16.3!

    Today, many users receive SI models that are not in DML format. They are given IBIS models, HSpice models, Spectre models as well as other generic SPICE models. We currently provide methods for translating these model formats into DML, but it's often not straightforward. It usually requires running...
    Posted to PCB Design (Weblog) by Jerry GenPart on Wed, Apr 21 2010
  • TeamAllegro Spices Up SNUG With Allegro PCB SI

    Allegro PCB SI has supported multiple simulation engines for well over seven years. Other than the native TLsim engine, HSpice has been one of the more popular simulation engine choices. This year at SNUG, we have been invited to meet with HSpice users and show them the value of running HSpice directly...
    Posted to PCB Design (Weblog) by TeamAllegro on Wed, Mar 24 2010
  • Allegro PCB SI Offers Out-of-the-Box IBIS 5.0 Support

    IBIS is sometimes known as the bird of knowledge, but is also the popular standard in modeling I/O buffers. Well, IBIS recently grew some big new wings when the 5.0 version of the spec was ratified. Those big wings include support for algorithmic modeling of SerDes transceivers. Instead of just modeling...
    Posted to PCB Design (Weblog) by Maxwell86 on Thu, Feb 11 2010
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