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  • Q&A: Jiayuan Fang Discusses Sigrity, Cadence Merger, Signal and Power Integrity, and 3D-ICs

    In July 2012 Cadence announced its acquisition of Sigrity , a leading provider of signal integrity (SI) and power integrity (PI) analysis tools for chip, package and board. Jiayuan Fang, Sigrity founder and CEO, joined Cadence as vice-president of R&D for high-speed design products in the Silicon...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 12 2012
  • Netlisting to PCB editor, Errors.

    Hi, Im a Student who has to Create a PCB board for an end of year project. Im trying to creat a netlist in OrCad to PCB editor but i have 24 errors. Most are saying somthing similar to: #21 ERROR(ORCAP-36036): Multiple pin 11's which have different nets connected for U1: SCHEMATIC1, PAGE1 (7.90,...
    Posted to PCB Design (Forum) by Lulaz on Tue, Dec 11 2012
  • PSPICE Simulation Error "Extra Text On Line"

    Hi, Working on an audio amplifier project for school and I'm trying to simulate the circuit in Pspice. When I actually go to run the simulation, I keep getting an "Extra Text On Line" error. Here's the output sim file: **** CIRCUIT DESCRIPTION **************************************...
    Posted to Cadence Academic Network (Forum) by luckyleo on Tue, Nov 27 2012
  • How Cadence Helps Universities Build EDA Infrastructures

    Many EDA companies, including Cadence, have university programs that make it easier for academia to acquire tools. But what about the software/hardware infrastructure that supports those tools? In this era of budget shortfalls, university compute infrastructures are under severe stress. Recently the...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Nov 7 2012
  • Numbering component in hierarchical block

    Good morning, I have an issue when designing hierarchical block with orcad capture 16.5 . I want to use hierarchical block because it help me to have a better view of the overall system. The problem is when I use hierarchical blocks the numebring component of cadence does not increment automatically...
    Posted to Feedback, Suggestions, and Questions (Forum) by damsBe on Thu, Oct 18 2012
  • Subcircuit Is Undefined Error

    When I try and simulate my circuit, which is just a buffer made up of two inverters back to back, I get the error messages shown below: WARNING -- Library file C:\Cadence\SPB_16.3\tools\PSpice\Library\infineon.lib has changed since index file nom.ind was created. WARNING -- The timestamp changed from...
    Posted to PCB Design (Forum) by KillaKem on Sat, Oct 6 2012
  • Allegro 16.6: Easing PCB Design for Multi-Gigabit/Second Signals

    Got a few picoseconds to spare? If you're a PCB designer working with a multi-Gbit/second serial link interface such as PCI Express 3.0 or a DDR memory interface, maybe not. Two new features in the Cadence Allegro 16.6 PCB design solution - announced today (Sept. 25, 2012) at PCB West - aim to help...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Sep 25 2012
  • dsn-files

    Hello everyone, can someone me show the structure of dsn-files or a place I can find them? The background is the following: I' ve build a project in Capture and then created a netlist. But on this procedure something seems to be going wrong. I could'nt load the original dsn-file nor the dbk-file...
    Posted to Logic Design (Forum) by wschira on Sat, Jul 14 2012
  • Why Cadence Bought Sigrity – And How it May Change PCB Analysis

    On July 2 Cadence announced its acquisition of Sigrity , a provider of signal integrity and power network analysis tools for PCB and IC package design. Cadence already has some technology in these areas, and many Allegro and OrCAD customers use Sigrity tools today. So why buy Sigrity, and why make this...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jul 12 2012
  • What's Good About Capture’s CIS INI Settings? Look to SPB16.5 and See!

    This week, I'm providing a very short blog. While the content is brief and simple, the positive impact to the Allegro Design Entry CIS usability is high! The Capture INI (project level) settings are always dynamic, the CIS settings are more or less static and usually do not change after the initial...
    Posted to PCB Design (Weblog) by Jerry GenPart on Fri, Jul 6 2012
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