Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> OrCAD Capture
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
OrCAD Capture
"capture CIS"
"PCB design"
.brd Viewer
.psm
0402
13
15.7
16
16.01
16.2
16.3
16.5
16.5 start page orcad capture
16.6
16.6 routing
allegro
Allegro 16.3
Allegro 16.5
Allegro 16.6
Allegro Design Entry
Allegro PCB Editor
Allegro System Architect (ASA)
AMS
AMS simulation
application note
applications
Appnote
ASA
Cadence
Capture
Capture CIS
Capture CIS'
Capture-CIS
CDNLive
ConceptHDL
Constraint Manager
Convergence
Cset
customer support
data management
dc
dc analysis
DEHDL
design
design data management
Design Entry
Design Entry CIS
Design Entry HDL
Design Reuse
Differential Pair Support
Digital SiP design
download
EDA360
edit symbol
electrical constraints
Footprint
Front-end PCB design
Grzenia
HDI
High Speed
High Speed design
High-Density Interconnect
IBIS
Industry Insights
layout
Librarians
libraries
Library
Library and design data management
Marketplace
OrCAD
OrCAD 16.3 16.5 Installation
OrCAD Capture Marketplace
OrCAD online store
OrCAD PCB Editor
OrCADapps
PCB
PCB Capture
PCB design
pcb editor
PCB Layout and routing
PCB SI
PCB Signal and power integrity
PCB Signal integrity
PSpice
Schematic
schematics
SI analysis and modeling
Signal Intregrity
SigXP UI
simulation
SPB
SPB 16.3
SPB16.01
SPB16.2
SPB16.3
SPB16.5
symbol
symbols
webinar
What's Good About Capture’s CIS INI Settings? Look to SPB16.5 and See!
This week, I'm providing a very short blog. While the content is brief and simple, the positive impact to the Allegro Design Entry CIS usability is high! The Capture INI (project level) settings are always dynamic, the CIS settings are more or less static and usually do not change after the initial...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Fri, Jul 6 2012
Capture CIS prompt:Please enter no more than 31 characters
Hello there,I'm newer about this forum. My question is that it warned "Please enter no more than 31 characters" when I create a new schematic page and renamed a long charater string more than 31 characters in Capture CIS.However,the number of character of page name could not be less than...
Posted to
PCB Design
(Forum)
by
WhiteSnow
on Thu, Jul 5 2012
Selective BOM
Is there any way to make certain components not appear in the schematic BOM, generated by Orcad ?
Posted to
PCB Design
(Forum)
by
Edumelara
on Thu, Apr 26 2012
What's Good About OrCAD Capture’s Find Result Report? Look to SPB16.5 and See!
The OrCAD Capture 16.5 release now has a method to generate a report (in CSV or HTML format) for the results from the Find command. Read on for more details… After you execute the Find command on a design, you can generate a report (in CSV or HTML format) for the results from the Find command...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Mon, Apr 23 2012
Way to vary pulse width of VPULSE
I'm using Orcap Capture CIS Lite tool version 16.5. I need a part that generates pulses and allows us to vary the pulse width. I did use VPULSE part and it generates a pulse with fixed duty cycle. Is there a way to vary the pulse width? If yes how? If not is there another part to use?
Posted to
PCB Design
(Forum)
by
SysEngr
on Fri, Mar 16 2012
What’s Good about OrCAD Apps? Symbol and Footprint Creation Just Got a Lot Easier!
Creating the symbols and footprints necessary to complete your designs can be a difficult task. Many designers utilize manual processes that are becoming unfeasible with the growing complexity of both the designs and the components used. Secondarily, manual processes are often error prone and provide...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, Feb 21 2012
Re: orcad 16.3 error "Pspice AD not Found"
no support from orcad ................ my friends thought is correct ........... i will try with other simulation softwares
Posted to
PCB Design
(Forum)
by
Karthick B
on Tue, Feb 21 2012
Whether ORCAD Capture16.5 supports to split a hierachical block into several section ,like the part
Hi I mean ,whether ORCAD Capture CIS 16.5 supports to split a hierachical block into serveral section like the part? Thanks A Lot
Posted to
PCB Design
(Forum)
by
rainmood
on Thu, Feb 16 2012
retain simulation trace
Hi Forum, I'm using Pspice/Capture to model a solar panel. I'm using some reasonable complicated simulation traces to analyse the system. What is frustrating is each time I adjust a parameter or the simulation profile, I have to re-input the formula for each trace. Is there anyway to automatically...
Posted to
PCB Design
(Forum)
by
SolarStudent
on Sat, Jan 7 2012
OrCAD PCB Designer "Lite" What are the limitations?
Happy New Year... I have been trying to find out what the limitations and differences are for the OrCAD PCB Designer "Lite". Is this a version that is marketed in the USA only? Is it the same as the Demo version available for download? And then: What are the limitations regarding number of...
Posted to
PCB Design
(Forum)
by
UlfK
on Mon, Jan 2 2012
Page 2 of 6 (56 items)
< Previous
1
2
3
4
5
Next >
...
Last »