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OVM,e,uvm
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Zocalo
UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar
Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e , SystemVerilog...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Thu, Oct 11 2012
Get Started on UVM-e with Free Introductory Video Tutorials
One of the many requests that we get from Specman/ e customers is that they would like some basic e tutorials. So, as a first step, Axel Scherer has recently posted 24, very short, byte sized UVM- e basic tutorials . Check them out. These e -based videos are targeted for design and verification engineers...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Thu, May 24 2012
Webinar Seeks to “End the Debate” – e or SystemVerilog?
Which language is best for functional IC verification - e or SystemVerilog? A newly archived Cadence webinar attempts to answer this question by analyzing the key capabilities in both languages, and presenting code comparisons that show how the same functionality would be expressed in either language...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 21 2011
Video: Update on AMIQ’s DVT IDE at DAC 2011 – Specman Debugger Integration, Open API
Specmaniacs and IES-XL users around the world know that Integrated Development Environment (IDE) and verification services provider AMIQ has been in the vanguard of supporting e RM, OVM, and now the full production UVM. At DAC 2011, AMIQ introduced a long awaited feature to DVT for Specmaniacs in particular...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Wed, Jun 22 2011
Video: Update on AMIQ’s DVT IDE and UVM 1.0 at DVCon 2011
The UVM 1.0 release was the big story of DVCon 2011, as it's the first verification methodology officially supported by all three of the "Big 3" simulation vendors. However, the very nature of the standard -- an open source library governed by a community similar in character to Linux itself...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Wed, Apr 6 2011
User View: Is e or SystemVerilog Best for Constrained-Random Verification?
Two main languages, both IEEE standards, are in use today for constrained-random verification - SystemVerilog and the e language. Which is best, under what circumstances? Geoffrey Faurie, a member of the Functional Verification Group at STMicroelectronics, has some definite opinions about that question...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jan 13 2011
2010 CDNLive Silicon Valley Photo Blog: Silicon Realization, ABV, OVM, MDV, Specman, Formal and More
If you are running short on time and can't view all the videos of the 2010 CDNLive Silicon Valley in San Jose, CA on October 26 posted here: www.cadence.com/cdnlive/na/2010/pages/default.aspx consider this photo blog as your very own "Cliff Notes" version. Click here to go to the gallery...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Tue, Nov 9 2010
DAC Report: Interview With AMIQ And Update On Their “DVT” IDE
One of the benefits of the Design Automation Conference is the opportunity to follow the growth trajectory of partner companies with each successive show. Last year our long time Verification Alliance partner AMIQ ( a name familiar to many Specmaniacs ) made their first appearance at DAC, and they were...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Wed, Jun 30 2010
UVM - 10 Years in the Making ...
In case you the missed the news today, the Accellera VIP TSC released the first version of the Universal Verification Methodology (UVM). This represents a significant achievement on the part of the TSC as it is the first standard SystemVerilog Base-Class Library and Methodology. While there has been...
Posted to
Functional Verification
(Weblog)
by
mstellfox
on Mon, May 17 2010
DVCon: Showcasing The Cadence Passion For Verification Excellence
Yeah, I know I'm a marketing guy but I really like this stuff! For sure, we are going tech-deep in our tutorials and papers, but we are also setting vision and direction for verification in our keynote presentation. For all of the details, visit our DVCon events page . Highlighted below are two of...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Mon, Feb 22 2010
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