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OVM,SystemVerilog,Accellera VIP TSC,VMM

  • TLM 2.0, UVM 1.0 and Functional Verification

    The DVCon 2011 conference was held this week and the Accellera Universal Verification Methodology (UVM) 1.0 release is breaking records in term of interest and attendance. UVM 1.0 is a big deal(!) The core functionality is solid and ready for deployment. Accellera held a full day tutorial on UVM 1.0...
    Posted to Functional Verification (Weblog) by Sharon on Mon, Mar 7 2011
  • "We Want UVM 1.0! When Do We Want it? Now!"

    Short of holding signs and yelling slogans, the 12 customers I visited in the past week all declared this mantra. All are planning to move to UVM 1.0 with all of them requiring the phasing and register package capabilities, but only one also requiring TLM2 support, primarily for accessing SystemC models...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 7 2010
  • DAC Cabbie Taught Me All I Need to Know About Verification

    Confidence from competence. Measurement through metrics. Sell without selling. These are the pearls I learned from my cab driver on the way home from DAC. Aside from the core truths they convey, they clearly define the top three verification items I saw at 47th DAC in Anaheim this year. Topping my list...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Mon, Jun 21 2010
  • The Future of OVM, VMM, and UVM

    In my last blog , I took a look back at the history of how we got to the first delivery of UVM. Now, let's take a look forward. Over the past week since UVM was released, and Cadence opened the UVMWorld portal to support the new UVM Community and ecosystem, I have seen a number of customers asking...
    Posted to Functional Verification (Weblog) by mstellfox on Mon, May 24 2010
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