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OVM,SystemC,e

UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e , SystemVerilog...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 11 2012
Challenging Misconceptions About Verification Languages

One thing I learned from the recent DVCon conference is that there are a number of common misconceptions about hardware verification languages (HVLs). I had a few of these myself. Two provocative and well-attended presentations provided a different way of looking at HVLs: "Apples Versus Apples HVL...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 10 2010
DVCon: Showcasing The Cadence Passion For Verification Excellence

Yeah, I know I'm a marketing guy but I really like this stuff! For sure, we are going tech-deep in our tutorials and papers, but we are also setting vision and direction for verification in our keynote presentation. For all of the details, visit our DVCon events page . Highlighted below are two of...

Posted to Functional Verification (Weblog) by Adam Sherilog on Mon, Feb 22 2010
Cadence Exec: Why Cadence is Comitted to e/Specman

In case you or your management are wondering about Cadence's commitment to supporting the e language and/or Specman technology, allow us to direct your attention to this interview of Cadence Verification VP Mitch Weaver (who never worked for Verisity, BTW) by industry analyst Richard Goering. As...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Feb 16 2010
DVCon 2010 For The Specmaniac

At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification technologies and methodologies ( full list of Cadence-sponsored activities is posted here ). Of course, Team Specman is here help Specmaniacs discover the many activities that will feature Specman and e language...

Posted to Functional Verification (Weblog) by teamspecman on Mon, Feb 15 2010
Adam’s Verification Top 10 In '10

I love top 10 lists. Not so much for the drama of the count-down, but for arguments that inevitably fall out of any prioritization. So here is my verification top 10 in '10, let the rants begin! 10. VHDL 1076-2009 Support . Huh? How did this get here? Given the breadth of IES (Incisive Enterprise...

Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Dec 29 2009
Formalizing Multilanguage Mixology For e Users

Historically it’s been very common for e users to have to mix other programming languages with their e verification environment. Some examples include adding C or C++ reference models, contributing e Universal Verification Components (UVCs) to non- e testbenches, or even interfacing to Matlab models...

Posted to Functional Verification (Weblog) by teamspecman on Thu, Dec 24 2009
UPDATE: EU ClubT's Start This Week!

Just a quick reminder that the ClubT series starts this week! Here are the specific dates and locations: Feldkirchen (Munich area), Germany on this Thursday October 15 Eindhoven, The Netherlands on this Friday October 16 Grenoble, France this coming Monday October 19 Bristol, UK next Wednesday October...

Posted to Functional Verification (Weblog) by teamspecman on Mon, Oct 12 2009
CDNLive San Jose 2009 for the Specmaniac

Even sooner than the EU ClubTs is CDNLive San Jose 2009 , where this year the event is a "hybrid" format of in-person workshops and on-line webinars. As with past CDNLive's, the agenda spans the entire Cadence product line, subdivided into tracks for the major segments of the design &...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 30 2009
EU Specmaniacs: ClubTs Are Coming in 2 Weeks!

EU-based Specmaniacs and "Trailblazers" rejoice: the annual ClubT series is back! As always, these free events feature direct contact with Cadence R&D and Methodology experts to share developments in advanced verification, updates to the "Trailblazer" program, and hear your emerging...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Sep 29 2009

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OVM,SystemC,e

UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Challenging Misconceptions About Verification Languages

DVCon: Showcasing The Cadence Passion For Verification Excellence

Cadence Exec: Why Cadence is Comitted to e/Specman

DVCon 2010 For The Specmaniac

Adam’s Verification Top 10 In '10

Formalizing Multilanguage Mixology For e Users

UPDATE: EU ClubT's Start This Week!

CDNLive San Jose 2009 for the Specmaniac

EU Specmaniacs: ClubTs Are Coming in 2 Weeks!