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OVM,SystemC,Industry Insights

  • At DVCon 2011 Next Week

    Next week my colleagues and I will be at DVCon 2011 in force, ready to regale you with technical papers, panels, and techtorials covering the full range of functional, assertion-based, mixed-signal, and transaction-level verification topics. If you are within a tank of gas or a Southwest flight of San...
    Posted to Functional Verification (Weblog) by jvh3 on Fri, Feb 25 2011
  • Accellera Approves UVM 1.0 – Bold Step Forward for Functional Verification

    There's big news today (Feb. 18) in the functional verification world. As noted in various tweets from standards group members, the Accellera standards organization board has unanimously approved the Universal Verification Methodology (UVM) 1.0 as an industry standard for verification interoperability...
    Posted to Industry Insights (Weblog) by rgoering on Fri, Feb 18 2011
  • Q&A: How CoFluent Eases Creation of SystemC Models

    SystemC transaction-level models (TLMs) are great for architectural exploration, but what do you do if you don't have all the models you need? CoFluent Design , a Cadence System Realization Alliance partner, offers an alternative with CoFluent Studio, a product that automatically generates SystemC...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 15 2010
  • Challenging Misconceptions About Verification Languages

    One thing I learned from the recent DVCon conference is that there are a number of common misconceptions about hardware verification languages (HVLs). I had a few of these myself. Two provocative and well-attended presentations provided a different way of looking at HVLs: "Apples Versus Apples HVL...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 10 2010
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