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OVM,OVM SV,OVM e,OOP

  • When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?

    A famous expression in the software world is that “you can only expect 10 good lines of production code per day”. Web search for this phrase and you will see there is ongoing debate whether this figure is still only 10 lines, or it’s improved to 20, or 100, or more. One thing that’s...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Mar 30 2010
  • DVCon 2010 - Day 3

    Click here or on the image below to go to the annotated photo blog of DVCon 2010 Day 3. The images and notes include highlights from: A paper on "Where OOP Falls Short of Verification Needs" (And there is also a video interview of Matan elaborating on the paper The paper "Tweak Free Reuse...
    Posted to Functional Verification (Weblog) by jvh3 on Tue, Mar 2 2010
  • DVCon 2010 - Day 2

    Click here or on the image below to go to the annotated photo blog of DVCon Day 2. Photos & notes include highlights from: Brett Lammers' paper on "Apples to Apples HVL Comparison Finally Arrives" Lunch panel on "OVM found the bugs, now how do we debug them faster" Cadence...
    Posted to Functional Verification (Weblog) by jvh3 on Fri, Feb 26 2010
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