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OVM,OVM SV,OVM e,Functional Verification

  • UVM - 10 Years in the Making ...

    In case you the missed the news today, the Accellera VIP TSC released the first version of the Universal Verification Methodology (UVM). This represents a significant achievement on the part of the TSC as it is the first standard SystemVerilog Base-Class Library and Methodology. While there has been...
    Posted to Functional Verification (Weblog) by mstellfox on Mon, May 17 2010
  • Inside Cadence: Training for EDA360

    Over the past few weeks all of Cadence's Verification and Systems Solutions Applications Engineers (AEs), Services Engineers, and many Customer Support staff, have been brought together for detailed methodology and product training. The objectives of this ambitious undertaking are to bring their...
    Posted to Functional Verification (Weblog) by jvh3 on Thu, May 6 2010
  • Informative Tweets on WHEN Inheritance

    Earlier today a lively and very instructive thread on the relative virtues of WHEN Inheritance developed on Twitter between @pmarriott (a D&V consultant in Montreal, Canada) , @yaron_think_ver (a verification consultant based in Israel) , and @teamspecman. Because this exchange was very technical...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, May 4 2010
  • When Less Is More, Part 2: Is e Code Really Up to 3x More Compact Than SystemVerilog?

    In my last post I wrote some packet generation code to validate the claim that e code can be up to 3 times more compact vs. the equivalent functionality in SystemVerilog. The result was actually an e description that was more than 3x less than the SystemVerilog equivalent. In this post, let’s see...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Apr 6 2010
  • When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?

    A famous expression in the software world is that “you can only expect 10 good lines of production code per day”. Web search for this phrase and you will see there is ongoing debate whether this figure is still only 10 lines, or it’s improved to 20, or 100, or more. One thing that’s...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Mar 30 2010
  • DVCon 2010 - Day 3

    Click here or on the image below to go to the annotated photo blog of DVCon 2010 Day 3. The images and notes include highlights from: A paper on "Where OOP Falls Short of Verification Needs" (And there is also a video interview of Matan elaborating on the paper The paper "Tweak Free Reuse...
    Posted to Functional Verification (Weblog) by jvh3 on Tue, Mar 2 2010
  • DVCon 2010 - Day 2

    Click here or on the image below to go to the annotated photo blog of DVCon Day 2. Photos & notes include highlights from: Brett Lammers' paper on "Apples to Apples HVL Comparison Finally Arrives" Lunch panel on "OVM found the bugs, now how do we debug them faster" Cadence...
    Posted to Functional Verification (Weblog) by jvh3 on Fri, Feb 26 2010
  • DVCon 2010 - Day 1

    Click here or on the image below to go to the photo blog of DVCon Day 1. While I've added descriptive captions to the images, allow me to address the FAQ: "How was the traffic on show floor?". My unscientific observation was that the floor was a little lighter than last year, but this was...
    Posted to Functional Verification (Weblog) by jvh3 on Wed, Feb 24 2010
  • Adam’s Verification Top 10 In '10

    I love top 10 lists. Not so much for the drama of the count-down, but for arguments that inevitably fall out of any prioritization. So here is my verification top 10 in '10, let the rants begin! 10. VHDL 1076-2009 Support . Huh? How did this get here? Given the breadth of IES (Incisive Enterprise...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Dec 29 2009
  • OVM Innovation Means Business

    Today, Cadence recognized it's OVM team for their innovative contribution to the Cadence enterprise starting in 2008. Why enterprise? To me, enterprise is the most exciting part because it underscore how the OVM has rallied all of Cadence verification around a common cause which has both polished...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Nov 3 2009
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