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OVM,Industry Insights,DVCon

  • DVCon Panelists: What Should Accellera Do Next With UVM?

    The Universal Verification Methodology (UVM) 1.0 standard has been released by Accellera, but (surprise, surprise) it's not perfect and more needs to be done. What's still missing, and what should Accellera do next? Most panelists and audience members at the DVCon conference March 1 appeared...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 2 2011
  • At DVCon 2011 Next Week

    Next week my colleagues and I will be at DVCon 2011 in force, ready to regale you with technical papers, panels, and techtorials covering the full range of functional, assertion-based, mixed-signal, and transaction-level verification topics. If you are within a tank of gas or a Southwest flight of San...
    Posted to Functional Verification (Weblog) by jvh3 on Fri, Feb 25 2011
  • Challenging Misconceptions About Verification Languages

    One thing I learned from the recent DVCon conference is that there are a number of common misconceptions about hardware verification languages (HVLs). I had a few of these myself. Two provocative and well-attended presentations provided a different way of looking at HVLs: "Apples Versus Apples HVL...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 10 2010
  • DVCon OVM Panelists: Easing The Debug Challenge

    The good news about the Open Verification Methodology ( OVM ) and the advanced verification techniques it supports is that verification engineers are now finding more bugs than ever. The bad news is that the bottleneck is shifting to debugging. What are we going to do with all those bugs? User and vendor...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 4 2010
  • DVCon Panel: Why Verification Engineers Are “Sleepless”

    I view a panel as successful when I leave the room knowing more than when I came in. Such was the case at the "What keeps you up at night" panel at DVCon Feb. 24, which offered some interesting, provocative, and in several cases surprising perspectives about challenges and solutions in IC design...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 1 2010
  • Q&A: How System Design And Verification Can Go “Mainstream”

    System design and verification are part of the RTL flow today, but a higher level of abstraction is now poised to enter the IC design mainstream, according to Ran Avinun, marketing group director for system design and verification at Cadence. In this interview he discusses trends in hardware/software...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Feb 18 2010
  • Q&A: Why The e Verification Language Is Alive And Well

    In spite of rumors about the decline of the e verification language, it's not only still alive but is thriving and growing, according to Mitch Weaver, corporate vice president for front-end verification at Cadence. In this pre-DVCon interview, he answers questions about Cadence and industry support...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Feb 16 2010
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