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Xilinx
Get Started on UVM-e with Free Introductory Video Tutorials
One of the many requests that we get from Specman/ e customers is that they would like some basic e tutorials. So, as a first step, Axel Scherer has recently posted 24, very short, byte sized UVM- e basic tutorials . Check them out. These e -based videos are targeted for design and verification engineers...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Thu, May 24 2012
Update to the OVM Register Package
OVM users have something new to give thanks for this holiday season -- an update to the OVM Register Package (new link!!). This package is used by novice and advanced users and embodies years of experience gathered through hundreds of SystemVerilog projects. The Cadence genIES team has been remiss since...
Posted to
Functional Verification
(Weblog)
by
Team genIES
on Tue, Nov 29 2011
At DVCon 2011 Next Week
Next week my colleagues and I will be at DVCon 2011 in force, ready to regale you with technical papers, panels, and techtorials covering the full range of functional, assertion-based, mixed-signal, and transaction-level verification topics. If you are within a tank of gas or a Southwest flight of San...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Fri, Feb 25 2011
What Does Silicon Realization Mean for Verification Engineers?
Last May , I posed a question about what EDA360 means for verification engineers. Yesterday we made an announcement about verification for Silicon Realization that is a big deal. We are delivering a lot of new technology with immediate and high value to verification engineers everywhere. My colleagues...
Posted to
Functional Verification
(Weblog)
by
tomacadence
on Tue, Jan 11 2011
Infinite Playbook for the Verification Superbowl
Its 4th and long, you're down by six, the clock is running out, and you are wary of a bug-blitz. What play do you call? With new approach defined by Silicon Realization, the updated Incisive Enterprise Simulator provides the new capabilities to finsh your drive, route the bugs, and win the verification...
Posted to
Functional Verification
(Weblog)
by
Team genIES
on Mon, Jan 10 2011
How Do You Debug Your Testbench when it Won’t Stand Still?
The task of debugging a simulation problem in your design can be a difficult and time consuming task. These days, the verification engineer must also be able to debug very complex SystemVerilog testbenches too. This becomes difficult because of their dynamic nature -- they just won’t stand still...
Posted to
Functional Verification
(Weblog)
by
jimkje
on Tue, Dec 14 2010
New Blog: All About Integrated formal, Simulation, and Assertion-Based Verification Technologies & Methodologies
End-users of Incisive Formal Verifier ("IFV"), Incisive Enterprise Verifier ("IEV"), or anyone interested in either "pure formal" verification, integrated formal analysis and simulation verification, and assertion-based verification (“ABV”) in general: have we got the blog...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Sun, Apr 11 2010
DVCon: Showcasing The Cadence Passion For Verification Excellence
Yeah, I know I'm a marketing guy but I really like this stuff! For sure, we are going tech-deep in our tutorials and papers, but we are also setting vision and direction for verification in our keynote presentation. For all of the details, visit our DVCon events page . Highlighted below are two of...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Mon, Feb 22 2010
DVCon 2010 For The Specmaniac
At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification technologies and methodologies ( full list of Cadence-sponsored activities is posted here ). Of course, Team Specman is here help Specmaniacs discover the many activities that will feature Specman and e language...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Mon, Feb 15 2010
Adam’s Verification Top 10 In '10
I love top 10 lists. Not so much for the drama of the count-down, but for arguments that inevitably fall out of any prioritization. So here is my verification top 10 in '10, let the rants begin! 10. VHDL 1076-2009 Support . Huh? How did this get here? Given the breadth of IES (Incisive Enterprise...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Tue, Dec 29 2009
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