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OVM,Functional Verification,OOP

  • At DVCon 2011 Next Week

    Next week my colleagues and I will be at DVCon 2011 in force, ready to regale you with technical papers, panels, and techtorials covering the full range of functional, assertion-based, mixed-signal, and transaction-level verification topics. If you are within a tank of gas or a Southwest flight of San...
    Posted to Functional Verification (Weblog) by jvh3 on Fri, Feb 25 2011
  • New UVM Book Is For You And U But Not Ewe

    A Practical Guide to Adopting the Universal Verification Methodology (UVM) is the first book published on the emerging Accellera UVM . Written by the main authors of the user guide in the UVM release, this book provides more details and extends the methodology to address system level challenges. Unlike...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Jul 21 2010
  • When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?

    A famous expression in the software world is that “you can only expect 10 good lines of production code per day”. Web search for this phrase and you will see there is ongoing debate whether this figure is still only 10 lines, or it’s improved to 20, or 100, or more. One thing that’s...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Mar 30 2010
  • DVCon 2010 - Day 3

    Click here or on the image below to go to the annotated photo blog of DVCon 2010 Day 3. The images and notes include highlights from: A paper on "Where OOP Falls Short of Verification Needs" (And there is also a video interview of Matan elaborating on the paper The paper "Tweak Free Reuse...
    Posted to Functional Verification (Weblog) by jvh3 on Tue, Mar 2 2010
  • DVCon 2010 - Day 2

    Click here or on the image below to go to the annotated photo blog of DVCon Day 2. Photos & notes include highlights from: Brett Lammers' paper on "Apples to Apples HVL Comparison Finally Arrives" Lunch panel on "OVM found the bugs, now how do we debug them faster" Cadence...
    Posted to Functional Verification (Weblog) by jvh3 on Fri, Feb 26 2010
  • Cadence Exec: Why Cadence is Comitted to e/Specman

    In case you or your management are wondering about Cadence's commitment to supporting the e language and/or Specman technology, allow us to direct your attention to this interview of Cadence Verification VP Mitch Weaver (who never worked for Verisity, BTW) by industry analyst Richard Goering. As...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Feb 16 2010
  • DVCon 2010 For The Specmaniac

    At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification technologies and methodologies ( full list of Cadence-sponsored activities is posted here ). Of course, Team Specman is here help Specmaniacs discover the many activities that will feature Specman and e language...
    Posted to Functional Verification (Weblog) by teamspecman on Mon, Feb 15 2010
  • Spanning the Globe to Bring You the Constant Variety of Verification

    Any sports fan living in the US during the 70's and 80's will remember the dramatic introduction to ABC television's " Wide World of Sports ": "Spanning the globe to bring you the constant variety of sport… the thrill of victory… and the agony of defeat…...
    Posted to Functional Verification (Weblog) by jvh3 on Mon, Oct 12 2009
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