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OVM-e

If Only Carl Friedrich Gauss had IntelliGen in 1850

The N-queens issue is a challenging but standard puzzle when it comes to the world of constraint solving. It's a generalization of the 8-queens puzzle, whose description can be found in detail in Wikipedia ( http://en.wikipedia.org/wiki/Eight_queens_puzzle .) The challenge is to place N queens on...

Posted to Functional Verification (Weblog) by teamspecman on Thu, Aug 18 2011
Full Sequence Coverage in a Single Line of e Code?

I was asked recently about how to easily collect coverage on the sequences generated by the verification environment. Since this question has come up before, I thought I would take this opportunity to write a short blog on how to quickly and easily collect coverage on generated sequences. A comprehensive...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Jun 28 2011
Performance Tips and Tricks: Coding e Ports for Enhanced Performance

This blog entry builds on last week's Tips and Tricks posting in which we discussed the usage of list.delete(0) in Tip 1. This week, we discuss a topic that is close to many users. Ports are used widely throughout the verification environment as one of the main mechanisms for interacting with HDL...

Posted to Functional Verification (Weblog) by teamspecman on Fri, Sep 3 2010
e Templates: A Nifty Way To Create Reusable Code

Hi All, An e template (known as a parameterized type in other programming languages) is a feature that has been around for several releases and can be a great way of creating re-usable code. Templates can be used anywhere a user would like to create a single re-useable object that might operate on different...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Aug 10 2010
e Verification Job Postings We’ve Seen

Specmaniacs between jobs: over the last few weeks we’ve seen job postings for verification engineering in general, and e/Specman expertise in specific, in the LinkedIn groups: “Experts in SystemVerilog/Specman/VERA/System C” “Think Verification” “HVL (SystemC/C++/Verilog...

Posted to Functional Verification (Weblog) by teamspecman on Fri, Aug 6 2010
DAC Report: Interview With AMIQ And Update On Their “DVT” IDE

One of the benefits of the Design Automation Conference is the opportunity to follow the growth trajectory of partner companies with each successive show. Last year our long time Verification Alliance partner AMIQ ( a name familiar to many Specmaniacs ) made their first appearance at DAC, and they were...

Posted to Functional Verification (Weblog) by jvh3 on Wed, Jun 30 2010
Specman, e, and EDA360

The EDA industry is all abuzz over the new vision paper "EDA360 - The Way Forward for Electronic Design" ; and for good reason - in 2010 the electronics world is finally starting to transform in ways that have been long anticipated by Specmaniacs and our "Trailblazer" program partners...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Jun 8 2010
UVM - 10 Years in the Making ...

In case you the missed the news today, the Accellera VIP TSC released the first version of the Universal Verification Methodology (UVM). This represents a significant achievement on the part of the TSC as it is the first standard SystemVerilog Base-Class Library and Methodology. While there has been...

Posted to Functional Verification (Weblog) by mstellfox on Mon, May 17 2010
IEEE P1647-2010 Call For Participation

Attention Specmaniacs: the IEEE 1647 working group is looking for a few additional volunteers to help develop the next version of the e language standard. In case you haven't seen the article from new Working Group chair Darren Galpin on the "Industry Insights" blog , or the call for participation...

Posted to Functional Verification (Weblog) by teamspecman on Tue, May 12 2009
Performance-Aware e Coding Guidelines – Part 5

In this last segment of the series on performance-aware coding, allow me to share with you two tips on improving the performance of Temporals. Temporals Performance Tip 1: Setup a "Synch Unit" If you don't already use a synch unit - I recommend you setup one up now. Here's why: the...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Apr 28 2009

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OVM-e

If Only Carl Friedrich Gauss had IntelliGen in 1850

Full Sequence Coverage in a Single Line of e Code?

Performance Tips and Tricks: Coding e Ports for Enhanced Performance

e Templates: A Nifty Way To Create Reusable Code

e Verification Job Postings We’ve Seen

DAC Report: Interview With AMIQ And Update On Their “DVT” IDE

Specman, e, and EDA360

UVM - 10 Years in the Making ...

IEEE P1647-2010 Call For Participation

Performance-Aware e Coding Guidelines – Part 5