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OVM e,OVM SV,Specman

  • UVM - 10 Years in the Making ...

    In case you the missed the news today, the Accellera VIP TSC released the first version of the Universal Verification Methodology (UVM). This represents a significant achievement on the part of the TSC as it is the first standard SystemVerilog Base-Class Library and Methodology. While there has been...
    Posted to Functional Verification (Weblog) by mstellfox on Mon, May 17 2010
  • Inside Cadence: Training for EDA360

    Over the past few weeks all of Cadence's Verification and Systems Solutions Applications Engineers (AEs), Services Engineers, and many Customer Support staff, have been brought together for detailed methodology and product training. The objectives of this ambitious undertaking are to bring their...
    Posted to Functional Verification (Weblog) by jvh3 on Thu, May 6 2010
  • Informative Tweets on WHEN Inheritance

    Earlier today a lively and very instructive thread on the relative virtues of WHEN Inheritance developed on Twitter between @pmarriott (a D&V consultant in Montreal, Canada) , @yaron_think_ver (a verification consultant based in Israel) , and @teamspecman. Because this exchange was very technical...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, May 4 2010
  • e Coding Made Easy with the “DVT” Integrated Development Environment

    Specmaniacs everywhere should be aware of a great, full-featured integrated development environment (IDE) available for e language coding from long time Verification Alliance partner AMIQ . In today's post, Team Specman invites the founder of AMIQ, Cristian Amitroaie, to tell us about this tool,...
    Posted to Functional Verification (Weblog) by teamspecman on Wed, May 6 2009
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